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參數(shù)資料
| 型號： | UDA1361 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 96 kHz sampling 24-bit stereo audio ADC |
| 中文描述： | 96千赫采樣24位立體聲音頻ADC |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 97K |
| 代理商： | UDA1361 |
2001 Jan 17
5
Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
FUNCTIONAL DESCRIPTION
System clock
The UDA1361TS accommodates master and slave
modes. The system devices must provide the system
clock regardless of master or slave mode. In the master
mode a system clock frequency of 256f
s
is required. In the
slave mode a system frequency of 256, 384, 512 or 768f
s
is automatically detected (for a system clock of 768f
s
the
sampling frequency must be limited to 55 kHz). The
system clock must be locked in frequency to the digital
interface input signals.
Input level
The overall system gain is proportional to V
DDA
, or more
accurately the potential difference between the reference
voltages V
VRP
and V
VRN
. The
1 dB input level at which
THD + N/S is specified corresponds to
1 dB(FS) digital
output (relative to the full-scale swing). With an input gain
switch, the input level can be calculated as follows:
at 0 dB gain:
at 6 dB gain:
In applications where a 2 V (RMS) input signal is used, a
12 k
resistor must be connected in series with the input
of the ADC. This forms a voltage divider together with the
internal ADC resistor and ensures that only 1 V (RMS)
maximum is input to the IC.
Usingthisapplicationfora2 V(RMS)inputsignal,thegain
switch must be set to 0 dB. When a 1 V (RMS) input signal
is input to the ADC in the same application the gain switch
must be set to 6 dB.
Anoverviewofthemaximuminputvoltageallowedagainst
the presence of an external resistor and the setting of the
gain switch is given in Table . The power supply voltage is
assumed to be 3 V.
Table 1
Application modes using input gain stage
Multiple format output interface
The serial interface provides the following data output
formats in both master and slave modes
(see Figs 3, 4 and 5).
I
2
S-bus with data word length of up to 24 bits
MSB-justifiedserial formatwith datawordlength ofupto
24 bits.
The master mode drives pins WS (word select; 1f
s
) and
BCK (bit clock; 64f
s
). WS and BCK are received in slave
mode.
Table 2
Master/slave select
Table 3
Select data format
Decimation filter
The decimation from 64f
s
is performed in two stages. The
first stage realizes a 4th-order sinx/x characteristic. This
filter decreases the sample rate by 8.
The second stage, a FIR filter, consists of 3 half-band
filters, each decimating by a factor of 2.
V
i
1 dB
–
(
)
V
----------------------------------
V
–
3
V (RMS)
=
=
V
i
1 dB
–
(
)
V
---------2
V
–
V (RMS)
=
=
RESISTOR
(12 k
)
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE (RMS)
Present
Present
Absent
Absent
0 dB
0 dB
0 dB
6 dB
2 V
1 V
1 V
0.5 V
MSSEL
MASTER/SLAVE SELECT
L
H
M
slave mode
master mode
(reserved for digital test)
SFOR
DATA FORMAT
I
2
S-bus data format
MSB-justified data format
(reserved for analog test)
L
H
M
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UDA1361TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:96 kHz sampling 24-bit stereo audio ADC |
| UDA1361TS/N1 | 制造商:NXP Semiconductors 功能描述:ADC STEREO AUDIO 24BIT 16SSOP 制造商:NXP Semiconductors 功能描述:ADC, STEREO, AUDIO, 24BIT, 16SSOP |
| UDA1361TS/N1,112 | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC ADC STEREO 7712 24BIT RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
| UDA1361TS/N1,118 | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC 24 BIT ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
| UDA1361TSDK-T | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC 24 BIT ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
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