參數(shù)資料
型號: UPA2751GR
廠商: NEC Corp.
英文描述: SWITCHING N-CHANNEL POWER MOSFET
中文描述: 開關(guān)N溝道功率MOSFET
文件頁數(shù): 1/12頁
文件大?。?/td> 108K
代理商: UPA2751GR
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
2001
MOS FIELD EFFECT TRANSISTOR
μ
PA2751GR
SWITCHING
N-CHANNEL POWER MOS FET
DATA SHEET
Document No.
Date Published
Printed in Japan
G15781EJ1V0DS00 (1st edition)
March 2002 NS CP(K)
PACKAGE DRAWING (Unit: mm)
1.27
0.12 M
6.0 ±0.3
4.4
0.40
+0.10
0.78 Max.
0
1
1
0.8
0.5 ±0.2
0
+
5.37 Max.
0.10
1
4
8
5
1
2
7, 8
3
4
5, 6
; Source 1
; Gate 1
; Drain 1
; Source 2
; Gate 2
; Drain 2
CH1
CH2
CH1
CH2
EQUIVALENT CIRCUIT
(1/2 circuit)
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
DESCRIPTION
The
μ
PA2751GR is asymmetrical dual N-Channel MOS
Field Effect Transistor designed for DC/DC converters of
notebook computers and so on.
FEATURES
Asymmetric dual chip type
Low on-state resistance, Low C
iss
CH1: R
DS(on)2
: 21.0 m
MAX. (V
GS
= 4.5 V, I
D
= 4.5 A)
C
iss
= 1040 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
CH2: R
DS(on)2
: 35.0 m
MAX. (V
GS
= 4.5 V, I
D
= 4.0 A)
C
iss
= 480 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
Built-in G-S protection diode
Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
μ
PA2751GR
PACKAGE
Power SOP8
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
CH1/CH2
CH1/CH2
CH1
CH2
CH1
CH2
CH1/CH2
CH1/CH2
CH1/CH2
CH1/CH2
CH1
CH1
CH2
CH2
V
DSS
V
GSS
I
D(DC)
I
D(DC)
I
D(pulse)
I
D(pulse)
P
T
P
T
T
ch
T
stg
I
AS
E
AS
I
AS
E
AS
30
±20
±9.0
±8.0
±36
±32
1.7
2.0
150
V
V
A
A
A
A
W
W
°C
°C
A
mJ
A
mJ
Drain Current (pulse)
Note1
Total Power Dissipation (1 unit)
Note2
Total Power Dissipation (2 unit)
Note2
Channel Temperature
Storage Temperature
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
–55 to + 150
9.0
8.1
8.0
6.4
Notes 1.
PW
10
μ
s, Duty cycle
1%
2.
T
A
= 25°C, Mounted on ceramic substrate of 2000 mm
2
x 1.6 mm
3.
Starting T
ch
= 25°C, V
DD
= 15 V, R
G
= 25
, V
GS
= 20
0 V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.
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