參數(shù)資料
型號: UPC1934GR-1JG
廠商: NEC Corp.
元件分類: DC/DC變換器
英文描述: DC-DC CONVERTER CONTROL IC
中文描述: 的DC - DC轉(zhuǎn)換器控制IC
文件頁數(shù): 14/20頁
文件大?。?/td> 140K
代理商: UPC1934GR-1JG
Data Sheet G13567EJ3V0DS00
14
μ
PC1934
3.5
ON/OFF Control
The ON/OFF control method of the output oscillation is to input the ON/OFF signal from ON as shown in Figure 3-3.
The PWM converter can be turned ON/OFF by controlling the level of the DTC pin. However, it is necessary to keep the
level of the FB
output high so that the timer latch does not start when the PWM converter is OFF. In this circuit example,
the FB
output level is controlled by controlling the level of the I
I
pin.
Figure 3-3 ON/OFF Control
(1) When ON is high: OFF status
Q
1
: ON
Q
2
: ON
DTC pin: High level
Output duty of PWM comparator: 0 %
Q
3
: ON
I
I
pin: Low level
FB output: High level
SCP comparator output: High level
Q is ON.
Timer latch stops.
(2) When ON
3
is low: ON status
Q
1
: OFF
Q
2
is OFF
C
1
is charged in the sequence of [V
REF
C
1
R
4
]
DTC pin voltage drops.
Soft start
Q
3
: OFF
I
I
pin: High level
FB output: Low level
SCP comparator output: Low level
Q: OFF
Charging C
DLY
starts (timer latch start).
Caution Keep the high-level voltage of the DTC pin at 1.6 V or higher and the low-level voltage of the I
I
pin
within (R6/(R5+R6))
V
REF
. The maximum voltage that is applied to the I
I
pin must be equal to or lower
than V
REF
.
3.6
Notes on Actual Pattern Wiring
When actually carrying out the pattern wiring, it is necessary to separate control-related grounds and power-related
grounds, and make sure that they do not share impedances as far as possible. In addition, make sure the high-frequency
impedance is lowered using capacitors and other components to prevent noise input to the V
REF
pin.
+
+
+
ON
Q
1
Q
2
Q
3
Q
PWM
comparator
DTC
R
2
V
REF
C
DLY
C
1
FB
DLY
R
1
V
O
R
5
R
6
V
REF
R
4
R
3
I
I
I
N
0.3 V
0.63 V
Error
amplifier
To output stage
Oscillation section
(common to each channel)
SCP comparator
(common to each channel)
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