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參數(shù)資料
| 型號： | UPC1935GR |
| 廠商： | NEC Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | DC-DC CONVERTER CONTROL IC |
| 中文描述： | 的DC - DC轉(zhuǎn)換器控制IC |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 185K |
| 代理商： | UPC1935GR |
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Data Sheet G13418EJ3V0DS00
19
μ
PC1935
3.5.3
Channel 3 (for inverted output)
The ON/OFF signal control method of the output oscillation of channel 3 is to input the ON/OFF signal from ON
3
as
shown in Figure 3-5. The PWM converter can be turned ON/OFF by controlling the level of the DTC
3
pin. However, it is
necessary to keep the level of the FB
3
output high so that the timer latch does not start when the PWM converter is OFF.
In this circuit example, the FB
3
output level is controlled by controlling the level of the I
I3
pin.
Because channel 3 supports an inverted converter, its PWM comparator logic is different from that of channels 1 and 2.
Figure 3-5 ON/OFF Control (channel 3: for inverted output)
(1) When ON
3
is high: OFF status
Q
31
: ON
→
Q
32
: ON
→
DTC
3
pin: High level
→
Output duty of PWM comparator: 0 %
Q
33
: ON
→
I
I3
pin: Low level
→
FB
3
output: High level
→
SCP comparator output: High level
→
Q
1
is ON.
→
Timer latch stops.
(2) When ON
3
is low: ON status
Q
31
: OFF
→
Q
32
is OFF.
→
C
31
is charged in the sequence of [V
REF
→
C
31
→
R
34
]
→
DTC
3
pin voltage drops.
→
Soft start
Q
33
: OFF
→
I
I3
pin: High level
→
FB
3
output: Low level
→
SCP comparator output: Low level
→
Q
1
: OFF
→
Charging C
DLY
starts (timer latch start).
Caution
Keep the high-level voltage of the DTC
3
pin at 1.6 V or higher and the low-level voltage of the I
I3
pin
within 0.3 V. The maximum voltage that is applied to the I
I3
pin must be equal to or lower than V
REF
.
–
–
+
+
–
–
+
ON
3
Q
31
Q
32
Q
33
Q
1
PWM comparator
SCP comparator
(common to each channel)
DTC
3
R
32
–V
O3
(Converter
output voltage)
V
REF
C
DLY
C
31
FB
3
DLY
R
31
V
REF
R
34
R
33
I
I3
0.3 V
0.63 V
Error
amplifier
To output stage
Oscillation section
(common to each channel)
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