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參數(shù)資料
| 型號(hào)： | UPC8105GR-E1 |
| 廠商： | NEC Corp. |
| 英文描述： | 400 MHz QUADRATURE MODULATOR FOR DIGITAL MOBILE COMMUNICATION |
| 中文描述： | 400 MHz的正交調(diào)制器的數(shù)字移動(dòng)通信 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | UPC8105GR-E1 |
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Data Sheet P10807EJ3V0DS00
6
μ
PC8105GR
×
2
from LO
in
÷
2 F/F
I
I
Q
Q
to MOD
out
PIN EXPLANATION
PIN NO.
ASSIGN-
MENT
SUPPLY
VOL. (V)
PIN
VOL.(V)
FUNCTION AND APPLICATION
EQUIPMENT CIRCUIT
13
GND
0
14
15
Power
Save
VP/S
Power save control pin can be
controlled ON/SLEEP state with
bias as follows;
16
V
CC
2.7 to
5.5
Supply voltage pin for modulator.
Internal regulator can be kept
stable condition of supply bias
against the variable temperature
or V
CC
.
EXPLANATION OF INTERNAL FUNCTION
BLOCK
FUNCTION/OPERATION
BLOCK DIAGRAM
90
°
PHASE
SHIFTER
Input signal from LO is send to digital
circuit of T-type flip-flop through frequency
doubler. Output signal from T-type F/F is
changed to same frequency as LO input
and that have quadrature phase shift, 0
°
,
90
°
, 180
°
, 270
°
. These circuits have
function of self phase correction to make
correctly quadrature signals.
BUFFER AMP.
Buffer amplifiers for each phase signals to
send to each mixers.
MIXER
Each signals from buffer amp. are
quadrature modulated with two double-
balanced mixers.
High accurate phase and amplitude inputs
are realized to good performance for image
rejection.
ADDER
Output signals from each mixers are added
with adder and send to final amplifier.
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
VP/S (v)
STATE
1.8 to 5.5
0 to 1.0
ON
SLEEP
15
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