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參數(shù)資料
| 型號(hào)： | UPD120N25TA-AT |
| 元件分類： | 固定正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器 |
| 英文描述： | 2.5 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PDSO5 |
| 封裝： | LEAD FREE, PLASTIC, SC-74A, 5 PIN |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 233K |
| 代理商： | UPD120N25TA-AT |
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μPD120Nxx Series
Chapter Title
R03DS0030EJ0400 Rev.4.00
Page 13 of 13
Apr 15, 2011
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected
wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH
(MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the
device when the input level is fixed, and also in the transition period when the input level passes through the
area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of
static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control
must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators
that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work benches
and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with
mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device.
Immediately after the power source is turned ON, devices with reset functions have not yet been initialized.
Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not
initialized until the reset signal is received. A reset operation must be executed immediately after power-on
for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for
each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while
the device is not powered. The current injection that results from input of such a signal or I/O pull-up power
supply may cause malfunction and the abnormal current that passes in the device at this time may cause
degradation of internal elements. Input of signals during the power off state must be judged separately for
each device and according to related specifications governing the device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD120N25TA-E2-AT | 2.5 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PDSO5 |
| UT7150-AE3-5-R | 5 V FIXED POSITIVE LDO REGULATOR, PDSO3 |
| UT7150-T92-B-B | 5 V FIXED POSITIVE LDO REGULATOR, BCY3 |
| UT7150-T92-B-K | 5 V FIXED POSITIVE LDO REGULATOR, BCY3 |
| UT7150-T92-C-B | 5 V FIXED POSITIVE LDO REGULATOR, BCY3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD120N25TA-E1 | 制造商:NEC 制造商全稱:NEC 功能描述:THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A) |
| UPD120N25TA-E1-A | 制造商:NEC 制造商全稱:NEC 功能描述:THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A) |
| UPD120N25TA-E1-AZ | 制造商:NEC 制造商全稱:NEC 功能描述:THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A) |
| UPD120N25TA-E2 | 制造商:NEC 制造商全稱:NEC 功能描述:THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A) |
| UPD120N25TA-E2-A | 制造商:NEC 制造商全稱:NEC 功能描述:THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A) |
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