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| 型號(hào)： | UPD161401 |
| 廠(chǎng)商： | NEC Corp. |
| 英文描述： | 256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| 中文描述： | 256色，1/80-DUTY LCD控制器/驅(qū)動(dòng)器，片內(nèi)RAM |
| 文件頁(yè)數(shù)： | 21/124頁(yè) |
| 文件大?。?/td> | 647K |
| 代理商： | UPD161401 |
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Data Sheet S15726EJ2V0DS
21
μ
PD161401
5.2 Display Data RAM
5.2.1
Display data RAM
This RAM stores dot data for display and consists of (101
×
80)
×
8 bits. Any address of this RAM can be accessed by
specifying an X address and a Y address.
Display data D
0
to D
15
transmitted from the CPU corresponds to the pixels on the LCD (refer to
Table 5
1
). If the
μ
PD161401 is used in a multi-chip configuration, restrictions on display data transfer are relaxed and display setting
can be performed relatively freely.
The CPU writes data to the display RAM via I/O buffers. This write operation is performed independently of an
operation to read signals for driving the LCD. Therefore, even if the display data RAM is asynchronously accessed,
adverse effects such as flickering do not occur or the current LCD screen.
Table 5
1. Display Data RAM
MSB
LSB
MSB
LSB
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Dot (R)
Dot (G)
Dot (B)
Dot (R)
Dot (G)
Dot (B)
Pixel 1
Pixel 2
LCD panel
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
Pixel 8
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
Pixel 8
00H
01H
02H
03H
04H
05H
06H
07H
5.2.2
An X address of the display data RAM is specified by using the X address register (R4) as shown in
Figure 5
5
.
If the X address increment mode (INC = 0: control register 2 (R1)) is used, the specified X address is incremented or
decremented by one each time display data is written. Whether the address is incremented or decremented is specified
by the XDIR flag of control register 2 (R1) as shown in
Table 5
2
.
In the increment mode, the X address is incremented up to 64H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 00H.
In the decrement mode, the X address is decremented to 00H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 64H.
When the 16-bit data bus is selected (BMOD = 0), only an even address can be specified. Moreover, when the 16-bit
data bus is selected, dummy data is required as shown in
Figure 5
3
.
X address circuit
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相關(guān)代理商/技術(shù)參數(shù) |
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| UPD161401P | 制造商:NEC 制造商全稱(chēng):NEC 功能描述:256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
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| UPD161602A | 制造商:NEC 制造商全稱(chēng):NEC 功能描述:360/396-OUTPUT TFT-LCD SOURCE DRIVER |
| UPD161602AP | 制造商:NEC 制造商全稱(chēng):NEC 功能描述:360/396-OUTPUT TFT-LCD SOURCE DRIVER |
| UPD161602B | 制造商:NEC 制造商全稱(chēng):NEC 功能描述:360/396-OUTPUT TFT-LCD SOURCE DRIVER |
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