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參數(shù)資料
| 型號： | UPD16312GB-3B4 |
| 廠商： | NEC Corp. |
| 英文描述： | 1/4- to 1/11-DUTY FIPTM VFD CONTROLLER/DRIVER |
| 中文描述： | 1/4-的1/11-DUTY FIPTM變頻控制器/驅(qū)動器 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 143K |
| 代理商： | UPD16312GB-3B4 |
4
PD16312
Pin Function
Symbol
Pin Name
Pin No
Description
D
IN
Data input
6
Input serial data at rising edge of shift clock, starting from the low
order bit.
D
OUT
Data output
5
Output serial data at the falling edge of the shift clock, starting
from low order bit. This is N-ch open-drain output pin.
STB
Strobe
9
Initializes serial interface at the rising or falling edge of the
PD16312. It then waits for reception of a command. Data input
after STB has fallen is processed as a command. While
command data is processed, current processing is stopped, and
the serial interface is initialized. While STB is high, CLK is
ignored.
CLK
Clock input
8
Reads serial data at the rising edge, and outputs data at the
falling edge.
OSC
Oscillator pin
44
Connect resistor to this pin to determine the oscillation frequency
to this pin.
Seg
1
/KS
1
to
Seg
6
/KS
6
High-voltage output
15 to 20
Segment output pins (Dual function as key source)
Seg
7
to Seg
11
High-voltage output
(segment)
21 to 25
Segment output pins
Grid
1
to Grid
6
High-voltage output (grid)
37 to 32
Grid output pins
Seg
12
/Grid
11
to
Seg
16
/Grid
7
High-voltage output
(segment/grid)
26, 28 to 31
These pins are selectable for segment or grid driving.
LED
1
to LED
4
LED output
42 to 39
CMOS output. +20 mA max.
KEY
1
to KEY
4
Key data input
10 to 13
Data input to these pins is latched at the end of the display cycle.
SW
1
to SW
4
Switch input
1 to 4
These pins constitute a 4-bit general-purpose input port.
V
DD
Logic power
14, 38
5 V 10 %
V
SS
Logic ground
7, 43
Connect this pin to system GND.
V
EE
Pull-down level
27
V
DD
35 V max.
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