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參數(shù)資料
| 型號(hào)： | UPD16430AGF-3B9 |
| 廠商： | NEC Corp. |
| 英文描述： | LJT 56C 48#20 8#16 PIN PLUG |
| 中文描述： | 1 / 2，1 / 3，1 / 4占空比LCD控制器/驅(qū)動(dòng) |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 130K |
| 代理商： | UPD16430AGF-3B9 |
μ
PD16430A
4
No.
Symbol
I/O
Output Type
Description
71
OSC
IN
I/O
CMOS
These pins serve to connect the resistors of the system clock RC oscillator.
72
OSC
OUT
70
100 k
OSC
IN
71
OSC
OUT
When several devices are used, connect as follows:
70
100 k
OSC
IN
71
OSC
OUT
70
OSC
IN
71
OSC
OUT
34
73
V
SS
—
—
GND pin for device.
74
SYNC
I/O
Nch
Synchronous signal I/O pin.
This pin is used to synchronize two or more
μ
PD16430A’s. At this time,
each chip must be wire-ORed and a pull-up resistor (5 k to 10 k
) is
required.
This pin must be pulled up even when only one
μ
PD16430A is used.
Open drain
75
STB
Input
—
Strobe signal input pin for device’s select signal and serial communica-
tions.
This pin serves to latch display RAM data outputs, set the command data
receive mode and initialize serial communications.
Serial communication is enabled when this signal is a logic low.
When this pin is a logic high, shift clocks that are input are ignored.
(1) Display RAM data output buffer latch function
The internal display RAM data output is latched to the output latch circuit
at the rising edge of the STB signal when the BUSY pin outputs a logic
high.
However, latch timing depends on the LATCH MD and LATCH flags.
The latch time is 504.5/f
OSC
.
When the BUSY signal is a logic low, latching can cause incorrect display.
(2) Command data receive mode setting
The command data receive mode is set by the rising edge of the STB
signal when the BUSY pin outputs a logic high.
Once the command data receive mode is set, the initial byte (8 bits) is
processed as a command.
The command data processing time is approximately 300 ns.
The BUSY signal does not change during this time.
(3) Serial communication is initialized by the rising edge or the falling edge
of the STB signal when the BUSY pin outputs a logic low.
Once serial communication is initialized, the command data receive mode
is started.
During command data decoding or display data RAM interrupt, the STB
signal interrupts processing and initializes serial communications. At this
time, all displays are turned off (LCDON flag is reset).
76
DATA
Input
—
This pin inputs serial data for serial communication at the rising edge of
the shift clock.
77
CLK
Input
—
This pin inputs a shift clock for serial communication. The signal is output
at the rising edge of the shift clock signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD16430CGF-3B9(A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD16431A | 制造商:NEC 制造商全稱:NEC 功能描述:1/2, 1/3, 1/4-DUTY LCD CONTROLLER/DRIVER |
| UPD16431AGC-7ET | 制造商:NEC 制造商全稱:NEC 功能描述:1/2, 1/3, 1/4-DUTY LCD CONTROLLER/DRIVER |
| UPD16431AGC-7ET (A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD16432B | 制造商:NEC 制造商全稱:NEC 功能描述:1/8, 1/15 DUTY LCD CONTROLLER/DRIVER |
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