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參數資料
| 型號： | UPD16434GF-001-3B9 |
| 廠商： | NEC Corp. |
| 英文描述： | 1/8, 1/16 DUTY LCD CONTROLLER/DRIVER |
| 中文描述： | 1 / 8，1 / 16稅LCD控制器/驅動 |
| 文件頁數： | 28/64頁 |
| 文件大?。?/td> | 314K |
| 代理商： | UPD16434GF-001-3B9 |
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Data Sheet S10299EJ4V0DS00
28
μ
PD16434
4.2 Chip Address Selection Function
In a multi-chip system configuration, the chip address selection function compares the chip address assigned to
each
μ
PD16434 (by CA0, CA1 inputs) in advance and the chip address information (2 bits) sent from the CPU in the
serial or parallel data format. Only the chip whose address coincides with the chip address information is seleceted
(enables command/data input/output).
Thus, the CPU need not send two or more chip select signals (/CS).
This function is unconditionally provided in the parallel interface mode. However, in the serial interface mode, this
function is provided, when D2(CAE) = 1 (at reset release), is specified.
(1) Parallel interface mode (refer to Figure 3–5 and Figure 3–6)
After the falling edge of the /CS, the data read into D1 (corresponds to CA1) and D0 (corresponds to CA0) at the
first falling edge of the /STB becomes the 2-bit chip address information.
The parallel interface is equivalent to that for the
μ
PD82C43 I/O expander. Therefore, the chip address
information (0 to 3) for the
μ
PD16434 can be obtained on the D1 and D0 lines at the falling edge of the /STB by
executing an output or input instruction for port 4 to port 7 of the
μ
PD82C43, when the
μ
PD50H is connected to the
μ
PD16434 using the
μ
PD82C43 interface function.
(2) Serial interface mode (refer to Figure 3–3 and Figure 3–4)
After the falling edge of the /CS, the data read in to SI at the rising edge of the 7th /SCK (corresponds to CA1)
and 8th /SCK (corresponds to CA0), that is the lower 2 bits of the first 8-bit serial data, becomes the chip
address information.
Remarks 1.
When a RESET is input, the chip address comparison data (data compared with CA1 and CA0) in the
μ
PD16434 is cleared to "00". Therefore, in multi-chip configuration, if the /CS is set to low
immediately after the RESET input is released, a chip whose CA1 and CA0 are set to "00" sets the
/BUSY to high, informing the CPU that the chip can be accessed.
If no chip address is sent, a chip whose CA1 and CA0 are "00" will be accessed.
2.
The following points must be noted for a multi-chip configuration system using the parallel interface;
when transferring the process from chip A, which has already been in the read mode to chip B, and
again selecting chip A after that, the data pointer must be set by the data pointer load command
reading data.
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