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參數(shù)資料
| 型號(hào)： | UPD16602 |
| 廠商： | NEC Corp. |
| 英文描述： | 312-OUTPUT TFT-LCD FULL COLOR DRIVER |
| 中文描述： | 312輸出的TFT - LCD全彩驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 134K |
| 代理商： | UPD16602 |
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9
μ
PD16602
(4) Relatonship
with HS and PL/NL
HS
PL/NL
CLK
SPR
(SPL)
t
HS-SETUP
t
HS-HOLD
t
HS-SP
Sampling period
0 1 2
0 1 2
26 27
Hi-Z
Output period
Caution
HS and PL/NL edges have no relationship with clock timing.
Timing Item
Symbol
Description
Horizontal synchronization
setup time
t
HS-SETUP
Setup time of PL/NL signal with respect to HS.
Secure 50 ns
MIN.
at least.
Horizontal synchronization
hold time
t
HS-HOLD
PL/NL hold time. Secure 250 ns
MIN.
at least.
The hold capacitance at this time is at common potential V
COM
, but the output
buffer does not reach V
COM
, and therefore sampling is not possible.
Sampling start time
t
HS-SP
Time for the output buffer to reach V
COM
(reset level).
Secure 1.0
μ
s
MIN
at least. Sampling is possible at this time.
Input the start pulse at this time.
These characteristics are specified by load constants of 50 k
+ 100 pF.
(5) Internal sampling delay
CLK
SP
1
SP
2
D
R0
to D
R3
(input)
D
G0
to D
G3
(input)
D
B0
to D
B3
(input)
t
d1
t
d1
t
d2
t
d2
Timing Duration
Symbol
Description
CLK-sampling pulse delay
t
d1
Delay time between CLK signal and rising edge of internal sampling pulse
SPn.
Input an analog image signal with a timing difference of t
d1
in order to secure
a sufficient sampling period.
Sampling pulse-CLK delay
t
d2
Delay time between CLK signal and falling edge of internal sampling pulse.
t
d1
is 22 ±5 ns and t
d2
is 14 ±5 ns (these are not guaranteed values).
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| UPD166020T1F | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:MOS INTEGRATED CIRCUIT |
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| UPD16602N | 制造商:NEC 制造商全稱:NEC 功能描述:312-OUTPUT TFT-LCD FULL COLOR DRIVER |
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