參數(shù)資料
型號(hào)： UPD16675AN-051
廠商： NEC Corp.
英文描述： 1/34, 1/36 DUTY LCD CONTROLLER/DRIVER
中文描述： 1 / 34，1 / 36稅LCD控制器/驅(qū)動(dòng)
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 252K
代理商： UPD16675AN-051
7
μ
PD16675A
1.2
Logic System (Continued)
Pin Symbol
Pin Name
Pin No.
I/O
Description
D
0
/DATA
Data bus/data
218
I/O
In parallel interface mode, this pin becomes the D
0
bit of the data bus.
In serial interface mode, it becomes the input/output
pin of the command and display data (3 states).
D
1
to D
5
Data bus
217 to 213
I/O
In parallel interface mode, these pins become the D
1
to D
5
bits of the data bus.
In serial interface mode, leave them open.
D
6
/CAE
Data bus/chip
address enable
212
I/O
In 8-bit parallel interface mode, this pin becomes the
D
6
bit of the data bus.
In 4-bit parallel interface and serial interface modes,
it becomes chip address enable. Also, at High level,
it becomes chip address valid; at Low level, chip
address invalid.
In 8-bit parallel interface, it becomes chip address
valid.
D
7
/NS
Data bus/nibble select
211
I/O
When the word select (WS) is High level, this bit
becomes the D
7
bit of the data bus.
When WS is Low level, it becomes the nibble select
(NS). When NS is High level, it becomes 4-bit
parallel interface. When NS is Low level, it becomes
serial interface.
In 4-bit parallel interface mode, data cannot be read
out.
_____________
Reset
210
I
At Low level, internal initialization is performed.
V
CHA
Boosting magnitude
switching
205
I
The boosting magnitude of the internal booster
circuit is switched over. At High level, it is switched
to 3X, while, at Low level, 2X.
DA
CHA
D/A converter
switching
202
I
Select whether to use the internal D/A converter for
temperature correction or not. At High level, this
circuit is used, at Low level, unused.
VEXT
Reference supply
switching
198
I
Selects the method for supplying the reference
power circuit. At High level, the circuit is supplied
externally; and, at Low level, internally.
SYNC
Synchronization
227
I/O
Input/output pin for synchronization.
Master mode: Output
Slave mode: Input
CS
0
to CS
2
Chip select
207 to 209
I
When used for multiple chips, these pins are used to
specify their addresses. They can be accessed only
when coinciding with b2 to b4 bits of the interface
control register.
OSC
IN
Oscillation pin
200
I
OSC
OUT
201
O
These pins are connected with the 1 M
resistor.
When using external oscillation, input it into the
OSC
IN
, leaving the OSC
OUT
open.
OSC
BRI
External clock for
blinks
199
I
Input pin of the 2-Hz external clock.
It internally divides this clock by 2 to generate 1 Hz
and make it the synchronizing signal for blinks.
相關(guān)PDF資料
PDF描述
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