參數(shù)資料
型號(hào): UPD16750
廠商: NEC Corp.
英文描述: 384-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 256-GRAY SCALES
中文描述: 384輸出的TFT - LCD源驅(qū)動(dòng)程序完全兼容256灰度
文件頁(yè)數(shù): 1/24頁(yè)
文件大?。?/td> 188K
代理商: UPD16750
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1998
MOS INTEGRATED CIRCUIT
μ
PD16750
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256-GRAY SCALES)
DATA SHEET
Document No. S13719EJ4V0DS00 (4th edition)
Date Published April 2000 NS CP (K)
Printed in Japan
The mark
shows major revised points.
DESCRIPTION
The
μ
PD16750 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is
based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216
colors by output of 256 values
γ
-corrected by an internal D/A converter and 8-by-2 external power modules.
Because the output dynamic range is as large as V
DD2
0.2 V to V
SS2
+ 0.2 V, level inversion operation of the LCD’s
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.
Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFT-
LCD panels and SXGA TFT-LCD panels. This driver is applicable to SXGA TFT-LCD panels by input display signal 2
systems (Clock divide).
FEATURES
CMOS level input
384 outputs
Input of 8 bits (gradation data) by 6 dots
Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter
Output dynamic range: V
DD2
– 0.2 V to V
SS2
+ 0.2 V
High-speed data transfer: f
CLK
= 40 MHz (internal data transfer speed when operating at 3.0 V)
Apply for dot-line inversion, n-line inversion and column line inversion
Output voltage polarity inversion function (POL)
Display data inversion function (POL21/22)
Logic power supply voltage (V
DD1
) : 3.3 V
±
0.3 V
Driver power supply voltage (V
DD2
) : 9.0 V
±
0.5 V
Low power control function (LPC)
ORDERING INFORMATION
Part Number
Package
μ
PD16750N-xxx
TCP (TAB package)
Remark
The TCP’s external shape is customized. To order the required shape, please contact one of our sales
representatives.
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