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參數(shù)資料
| 型號(hào)： | UPD16878 |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動(dòng)電路 |
| 文件頁(yè)數(shù)： | 9/32頁(yè) |
| 文件大?。?/td> | 242K |
| 代理商： | UPD16878 |
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Data Sheet S15974EJ1V0DS
9
μ
PD16878
5. INTERFACE (I/F) CIRCUIT DATA CONFIGURATION (f
CLK
= 4-MHz EXTERNAL CLOCK INPUT)
Input data consists of serial data (8 bytes x 8 bits).
Input serial data with the LSB first, from the 1st byte to 8th byte.
(1) Initial data (2) Standard data
<1st byte> <1st byte>
Bit
Data
Function
Setting
Bit
Data
Function
Setting
D7
1
HEADER DATA2
D7
0
HEADER DATA2
D6
1
HEADER DATA1
D6
0
HEADER DATA1
D5
1
HEADER DATA0
DATA selection
D5
0
HEADER DATA0
DATA selection
D4
0
D4
0
D3
1 or 0
EXP3
Hi-Z or L
D3
1 or 0
EXP3
Hi-Z or L
D2
1 or 0
EXP2
Hi-Z or L
D2
1 or 0
EXP2
Hi-Z or L
D1
1 or 0
EXP1
Hi-Z or L
D1
1 or 0
EXP1
Hi-Z or L
D0
1 or 0
EXP0
Hi-Z or L
D0
1 or 0
EXP0
Hi-Z or L
Remark
Hi-Z : High impedance,
L : Low level (current sink)
Remark
Hi-Z : High impedance,
L : Low level (current sink)
<2nd byte>
<2nd byte>
Bit
Data
Function
Setting
Bit
Data
Function
Setting
D7
D7
1 or 0
α
ROTATION
α
ch CCW/CW
D6
D6
1 or 0
α
ENABLE
α
ch ON/OFF
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
8-bit data
input
Note
First Point Wait
Start point wait
8
μ
s to 2.04 ms
Setting
(1 to 255)
t = 8
μ
s
D0
6-bit data
input
α
Pulse Number
α
ch
Number of
pulses in 1 VD
Setting (0 to 63)
n = 2 pulses
Note
Note
Input other than
“
0
”
.
Note
The number of pulses can be varied in 2-pulse
steps.
<3rd byte>
<3rd byte>
Bit
Data
Function
Setting
Bit
Data
Function
Setting
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
8-bit data
input
Note
First Point
Magnetize Wait
Start point drive
wait
8
μ
s to 2.04 ms
Setting
(1 to 255)
t = 8
μ
s
D0
15-bit data
Low-order
8-bit data
input
α
Pulse Width
α
ch pulse
cycle
0.25 to 8191.75
μ
s
Setting
(1 to 32767)
t = 0.25
μ
s
Note
Input other than
“
0
”
.
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