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參數(shù)資料
| 型號(hào)： | UPD16878GS-BGG |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動(dòng)電路 |
| 文件頁(yè)數(shù)： | 25/32頁(yè) |
| 文件大?。?/td> | 242K |
| 代理商： | UPD16878GS-BGG |
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D
2
μ
P
T
Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low
to high, and at the falling edge of FF2 when the level changes from high
to low.
2. FF7 is an output signal that is used to check for the presence or absence
of a pulse in the standard data, is updated at the rising edge of LATCH
and reset once at the falling edge of LATCH. If CHECK SUM is other than
“
00H
”
, FF7 goes low, inhibiting pulse output, even if a pulse is generated.
3. CHECK SUM output is updated at the rising edge of LATCH.
RESET
V
D
LATCH
DATA
OSC
OUT
(original oscillation)
Start point wait
(FF1)
Start point wait +
start point drive wait
(FF2)
ENABLE OUT
Note 1
Chopping pulse
EXP0 to EXP3
PULSE OUT
PULSE GATE
(FF3)
PULSE CHECK
Note 2
(FF7)
CHECK SUM
Note 3
SCLK
SDATA
8th byte
1st byte
Initialization
Initial
I
1
Standard
S
1
Standard
EXP : 1
ENABLE: 1
S
2
Dummy data
EXP: 1
EXP : 0
ENABLE: 0
Standard
EXP : 0
ENABLE: 1
S
4
Standard
S
5
EXP : 1
ENABLE: 0
Standard
EXP : 1
error DATA
S
3
Input at rising
edge of RESET
Output by
I1 data
Output by chopping
setting of I1 data
Output by EXP
setting of I1 data
Output by EXP
setting of S1 data
Output by EXP
setting of S2DATA
Output by
I1 data
Output by S2
data setting
Output by S5
data setting
S
2
DATA output
Pulse error
Enable
S
4
DATA output
Outputs high level while
pulse is being generated
Outputs high level for standard data while a
pulse output signal exists (LATCH cycle)
High level because
data is normal.
Low level because
data is abnormal.
Restore to high level because
data is normal.
No pulse output because
data is erroneous
D0
D7
D6
D5
D4
D3
D2
D1
(LSB)
Data is held at rising edge of SCLK.
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