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參數(shù)資料
| 型號： | UPD16879GS-BGG |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動電路 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 199K |
| 代理商： | UPD16879GS-BGG |
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Data Sheet S14188EJ1V0DS00
15
μ
PD16879
I/F CIRCUIT DATA CONFIGURATION (f
CLK
= 4.5 MHz EXTERNAL CLOCK INPUT)
Input data consists of serial data (8 bits
×
13 bytes).
Input serial data with the LSB first, from the first byte to 13th byte.
[1st byte]
[2nd byte]
Bit
Data
Function
Setting
Bit
Data
Function
Setting
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
8 bit data
input
Note
First point
wait
First point wait
227.6
μ
s to
58.03 ms
Setting
(1 to 255)
t = 227.6
μ
s
D0
8 bit data
input
Note
First point
magnetize
wait
First point
magnetize
wait
227.6
μ
s to
58.03 ms
Setting
(1 to 255)
t = 227.6
μ
s
Note
Input other than “0”
Note
Input other than “0”
[3rd byte]
[4th byte]
Bit
Data
Function
Setting
Bit
Data
Function
Setting
D7
1 or 0
EXP1
Z/L
Note 1
D7
1 or 0
Power save
OFF/ON
Note 1
D6
1 or 0
EXP0
Z/L
Note 1
Bit
Data
EXT
α
Output
EXT
β
Output
D5
D6
Note 5
Enable
Note 2
Enable
Note 2
D4
D5
Note 5
Rotation
Note 3
Rotation
Note 3
D3
D4
Note 5
Pulse out
Pulse out
D2
D3
Note 5
FF7
FF7
D1
D2
Note 5
FF3
FF3
D0
6 bit data
input
Chopping
frequency
Chopping
frequency
35.71 kHz to
225 kHz
Setting
(8 to 48)
Note 2
D1
Note 5
Checksum
Note 4
FF2
D0
Note 5
Chopping
FF1
Notes 1.
Z: High impedance/L: low level
2.
0 to 7 input: PWM and pulse out nothing
49 to 63 input: 225 kHz fixed
Refer to 4 page
Notes 1.
Data “1”: Normal/Data “0”: Power save
2.
High: Conducts/Low: Stops
3.
High: Reverse (CCW)/Low: Forward (CW)
4.
High: Normal data/Low: Error data
5.
Select one of D0 to D6 and input ”1”.
If two or more of D0 to D6 are selected,
they are positively ORed for output.
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