9
μ
PD17062
17. D/A CONVERTER ....................................................................................................................... 217
17.1
PWM PINS .......................................................................................................................................
217
18. PLL FREQUENCY SYNTHESIZER ............................................................................................. 219
18.1
PLL FREQUENCY SYNTHESIZER CONFIGURATION .................................................................
18.2
OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK ..............................................
18.3
PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER...................................
18.4
REFERENCE FREQUENCY GENERATOR (RFG) ..........................................................................
18.5
PHASE COMPARATOR (
φ
-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK.........
18.6
PLL DISABLE MODE.......................................................................................................................
18.7
SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER ....................................................
219
220
221
223
225
231
232
19. A/D CONVERTER ....................................................................................................................... 233
19.1
PRINCIPLE OF OPERATION...........................................................................................................
19.2
D/A CONVERTER CONFIGURATION ...........................................................................................
19.3
REFERENCE VOLTAGE SETTING REGISTER (ADCR) ................................................................
19.4
COMPARISON REGISTER (ADCCMP) ..........................................................................................
19.5
ADC PIN SELECT REGISTER (ADCCHn) ......................................................................................
19.6
EXAMPLE OF A/D CONVERSION PROGRAM ............................................................................
233
234
235
235
236
237
20. IMAGE DISPLAY CONTROLLER ............................................................................................... 240
20.1
SPECIFICATION OVERVIEW AND RESTRICTIONS ....................................................................
20.2
DIRECT MEMORY ACCESS ...........................................................................................................
20.3
IDC ENABLE FLAG .........................................................................................................................
20.4
VRAM ...............................................................................................................................................
20.5
CHARACTER ROM ..........................................................................................................................
20.6
BLANK, R, G, AND B PINS ............................................................................................................
20.7
SPECIFYING THE DISPLAY START POSITION ...........................................................................
20.8
SAMPLE PROGRAMS ....................................................................................................................
240
243
245
246
255
263
264
268
21. HORIZONTAL SYNC SIGNAL COUNTER ................................................................................ 274
21.1
HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION ....................................................
21.2
GATE CONTROL REGISTER (HSCGT)..........................................................................................
21.3
HSYNC COUNTER (HSC) ...............................................................................................................
21.4
EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL..........................................................
274
275
276
276
22. INSTRUCTION SETS .................................................................................................................. 277
22.1
OUTLINE OF INSTRUCTION SETS...............................................................................................
22.2
INSTRUCTIONS ..............................................................................................................................
22.3
LIST OF INSTRUCTION SETS .......................................................................................................
22.4
BUILT-IN MACRO INSTRUCTIONS ..............................................................................................
277
278
279
281
23. RESERVED SYMBOLS FOR ASSEMBLER ............................................................................... 282
23.1
SYSTEM REGISTER (SYSREG) .....................................................................................................
23.2
DATA BUFFER (DBF) ......................................................................................................................
23.3
PORT REGISTER .............................................................................................................................
23.4
REGISTER FILES .............................................................................................................................
282
282
283
284