參數(shù)資料
型號: UPD17149
廠商: NEC Corp.
英文描述: SMALL, GENERAL-PURPOSE 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 小,通用4位單晶片微控制器
文件頁數(shù): 31/102頁
文件大?。?/td> 408K
代理商: UPD17149
31
μ
PD17145(A1), 17147(A1), 17149(A1)
11.2 Port 0B (P0B
0
, P0B
1
, P0B
2
, P0B
3
)
Port 0B is a 4-bit I/O port with an output latch. It is mapped at address 71H of BANK0 of the data memory.
The output format is CMOS push-pull output.
This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0BGIO
(bit 1 of address 2CH) on the register file.
When P0BGIO = 0, all the pins of port 0B are set in the input mode. When an instruction that reads the data
of the port register is executed at this time, the pin status is read.
When P0BGIO = 1, all the pins of port 0B are set in the output mode, and the contents written to the output
latch are output to the pins. When an instruction that reads the port status is executed with the port set in the
output mode, the contents of the output latch, instead of the pin status, are read.
A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is
connected is specified by P0BGPU (bit 1 at address 0CH) of the register file. All the four-bit pins are pulled
up when P0BGPU = 1. When P0BGPU = 0, the pull-up resistor is not connected.
P0BGIO and P0BGPU are cleared to “0” at reset, and all the P0B pins are set in the input mode without the
pull-up resistor connected. The value of the output latch is also cleared to “0”.
Table 11-2. Writing and Reading Port Register (0.71H)
P0BGIO
Input/Output
BANK0 71H
RF: 2CH, bit 1
Mode of Pin
Write
Read
0
Input
Enabled
P0B pin status
1
Output
Write to P0B latch
P0B latch contents
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