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μ
PD17215, 17216, 17217, 17218
47
Table 8-2 Operations After HALT Mode Release (2/2)
(b)
HALT 02H
HALT Mode Released by:
Interrupt Status
Interrupt Enable Flag
Operations after HALT Mode Release
Disabled
DI
Enabled
8-Bit Timer
Disabled
EI
Enabled
Branches to interrupt vector address
8.2
HALT Instruction Execution Conditions
The HALT instruction can be executed, only under special conditions, as shown in Table 8-3, to prevent the program
from hangup.
If the conditions in Table 8-3 are not satisfied, the HALT instruction is treated as an NOP instruction.
Table 8-3 HALT Instruction Execution Conditions
Operand Value
Execution Conditions
0010B (02H)
When all interrupt request flags (IRQTM) of 8-bit timer are reset
<1> When interrupt request flag is reset, corresponding to interrupt whose interrupt enable
flag (IPTM, IPBTM, or IP) is set
<2> When high level is input to all P0A
0
-P0A
3
and P0B
0
-P0B
3
pins
1000B (08H)
Other Than Above
Inhibited
8.3
STOP Mode
In the STOP mode, the system clock (f
x
) oscillation is stopped and the program execution is stopped to minimize current
dissipation.
To set the STOP mode, use the STOP instruction.
The STOP mode releasing condition can be specified by the STOP instruction operand, as shown in Table 8-4.
After the STOP mode has released, the operation is performed as follows:
<1> Resets IRQTM.
<2> Starts the basic interval timer and watchdog timer (does not reset).
<3> Resets and starts the 8-bit timer.
<4> Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter coincides with the
value of the modulo register (IRQTM is set).
Instructions are executed from the
instruction next to the HALT
instruction.
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