Data Sheet U14360EJ1V0DS00
μ
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
29
3.
PORTS
3.1
Port 0A (P0A
0
through P0A
3
)
This is a 4-bit input port. Data is read through port register P0A (address 70H of BANK0). This port is a CMOS
input port with a pull-up resistor, and can be used for key return input for a key matrix.
In the standby mode, the standby status is released when a low level is input to at least one of these pins.
3.2
Port 0B (P0B
0
through P0B
3
)
This is a 4-bit I/O port which can be set in the input or output mode in 1-bit units by using P0BBIO (address 26H)
of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as key source lines of a key
matrix.
The data input to this port can be read or the data output from this port can be set by using the P0B register (address
71H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 k
is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
On reset, this port is set in the input mode.
3.3
Port 0C (P0C
0
through P0C
3
)
This is a 4-bit I/O port which can be set in the input or output mode in 4-bit units (group I/O) by using P0CDGIO
(bit 2 of address 37H) of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as key source lines of a key
matrix.
The data input to this port can be read or the data output from this port can be set by using the P0C register (address
72H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 k
is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
On reset, this port is set in the output mode and outputs low.
3.4
Port 0D (P0D
0
through P0D
3
)
This is a 4-bit I/O port which can be set in the input or output mode in 4-bit units (group I/O) by using P0CDGIO
(bit 3 of address 37H) of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as key source lines of a key
matrix.
The data input to this port can be read or the data output from this port can be set by using the P0D register (address
73H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 k
is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
On reset, this port is set in the output mode and outputs low.