參數(shù)資料
型號(hào): UPD23C128040BLGX-xxx
廠商: NEC Corp.
英文描述: 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD BY 8-BIT (BYTE MODE) / 8M-WORD BY 16-BIT (WORD MODE) PAGE ACCESS MODE
中文描述: 128兆位掩膜可編程ROM的1,600字的8位(字節(jié)模式)/ 800萬(wàn)字由16位(字模式)頁(yè)面訪問(wèn)模式
文件頁(yè)數(shù): 13/24頁(yè)
文件大?。?/td> 266K
代理商: UPD23C128040BLGX-XXX
Data Sheet M16048EJ2V0DS
13
μ
PD23C128040BL, 23C128080BL
Read Cycle Timing Chart 2 (Page Access Mode)
(Input)
/CE
(Input)
/OE or OE (Input)
t
ACC
Data Out
t
CE
t
OE
t
PAC
Note 5
t
PAC
Note 5
O0 to O7,
O8 to O15
Note 4
(Input)
(Output)
Data Out
Data Out
High-Z
High-Z
t
OH
t
OH
t
OH
t
DF
Note 3
A2 to A22
A3 to A22
Upper address
Note 1
A
1
Note 2
, A0, A1
A
1
Note 2
, A0, A1, A2
Page address
Note 1
Notes 1.
The address differs depending on the product as follows.
Part Number
Upper address
Page address
μ
PD23C128040BL
A2 to A22
A–1, A0, A1
μ
PD23C128080BL
A3 to A22
A–1, A0, A1, A2
2.
During WORD mode, A–1 is O15.
3.
t
DF
is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
4.
During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5.
The definition of page access time is as follows.
[
μ
PD23C128040BL ]
Page access time
Upper address (A2 to A22)
/CE input condition
/OE or OE input condition
inputs condition
t
PAC
Before t
ACC
– t
PAC
Before
t
CE
– t
PAC
Before stabilizing of page
address (A–1, A0, A1)
[
μ
PD23C128080BL ]
Page access time
Upper address (A3 to A22)
/CE input condition
/OE or OE input condition
inputs condition
t
PAC
Before t
ACC
– t
PAC
Before
t
CE
– t
PAC
Before stabilizing of page
address (A–1, A0, A1, A2)
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