參數(shù)資料
型號： UPD30181AYF1-131-GA3
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數(shù)： 45/72頁
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3
Data Sheet U16277EJ1V0DS
45
μ
PD30181A, 30181AY
(1) Clock parameters
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
CLKSEL(2:0) = 111
Note
147.4
MHz
CLKSEL(2:0) = 110
131.1
MHz
CLKSEL(2:0) = 101
118.0
MHz
CLKSEL(2:0) = 100
98.3
MHz
CLKSEL(2:0) = 011
90.7
MHz
CLKSEL(2:0) = 010
84.1
MHz
CLKSEL(2:0) = 001
78.5
MHz
CPU core operating
frequency
f
AClock
CLKSEL(2:0) = 000
73.7
MHz
DIVMODE(1:0) = 11
Note
18.432
f
AClock
/1
65.55
MHz
DIVMODE(1:0) = 10
18.432
f
AClock
/2
65.55
MHz
DIVMODE(1:0) = 01
18.432
f
AClock
/3
65.55
MHz
TClock, SDCLK
frequency
f
TClock
DIVMODE(1:0) = 00
Note
18.432
f
AClock
/4
65.55
MHz
MasterOut frequency
f
MasterOut
f
TClock
/4
MHz
PCICLKDIV(1:0) = 00
f
TClock
/8
32.78
MHz
PCICLKDIV(1:0) = 01
f
TClock
/4
32.78
MHz
PCICLKDIV(1:0) = 10
Note
f
TClock
/2
32.78
MHz
PCIClock frequency
t
PCIClock
PCICLKDIV(1:0) = 11
Note
f
TClock
/1
32.78
MHz
LCLKDIV(1:0) = 11
Note
f
TClock
/1
MHz
LCLKDIV(1:0) = 01
f
TClock
/2
MHz
LCLKDIV(1:0) = 10
f
TClock
/3
MHz
LClock frequency
f
LClock
LCLKDIV(1:0) = 00
f
TClock
/4
MHz
PCLKDIV(1:0) = 00
18.432
f
TClock
/1
32.78
MHz
PCLKDIV(1:0) = 01
18.432
f
TClock
/2
32.78
MHz
PCLKDIV(1:0) = 10
18.432
f
TClock
/4
32.78
MHz
PClock frequency
f
PClock
PCLKDIV(1:0) = 11
Note
18.432
f
TClock
/8
32.78
MHz
ECUSYSCLKDIV(1:0) = 00
Note
f
TClock
/1
32.78
MHz
ECUSYSCLKDIV(1:0) = 01
f
TClock
/2
32.78
MHz
ECUSYSCLKDIV(1:0) = 10
f
TClock
/4
32.78
MHz
ECU_SysClock
frequency
f
ECU_SysClock
ECUSYSCLKDIV(1:0) = 11
f
TClock
/8
32.78
MHz
Note
These values cannot be set in the current V
R
4181A.
Remarks 1.
The settings of the CLKSEL(2:0) and DIVMODE(1:0) signals are sampled when the RTCRST# signal
changes to high level.
2.
PCICLKDIV(1:0): Bits 9 and 8 of the CLKDIVCTRL register in the CCU. Set these bits before
starting use of the on-chip peripheral PCI unit.
3.
LCLKDIV(1:0): Bits 5 and 4 of the EXIBUCFG register in the EXIBU. Set these bits before setting
the timing parameters for each register of the EXIBU.
4.
PCLKDIV(1:0): Bits 1 and 0 of the CLKDIVCTRL register in the CCU.
5.
ECUSYSCLKDIV(1:0): Bits 5 and 4 of the CLKDIVCTRL register in the CCU. Set these bits before
starting use of the ECU.
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