參數(shù)資料
型號： UPD44324182F5-E40-EQ2
廠商： NEC Corp.
元件分類： DRAM
英文描述： 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
中文描述： 36M條位SRAM的2條DDRII字爆發(fā)運(yùn)作
文件頁數(shù)： 14/32頁
文件大?。?/td> 349K
代理商： UPD44324182F5-E40-EQ2
14
Preliminary Data Sheet
M16780EJ1V0DS
μ
PD44324082, 44324092, 44324182, 44324362
DC Characteristics (T
A
= 0 to 70°C, V
DD
= 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Note
x8, x9 x18
x36
Input leakage current
I
LI
–2
–
+2
μ
A
I/O leakage current
I
LO
–2
–
+2
μ
A
Operating supply current
I
DD
V
IN
≤
V
IL
or V
IN
≥
V
IH
,
–E33
750 1,050 1,200
mA
(Read Write cycle)
I
I/O
= 0 mA
–E40
650
900 1,000
Cycle = MAX.
–E50
550
750
850
Standby supply current
I
SB1
V
IN
≤
V
IL
or V
IN
≥
V
IH
,
–E33
550
mA
(NOP)
I
I/O
= 0 mA
–E40
500
Cycle = MAX.
–E50
400
High level output voltage
V
OH(Low)
|I
OH
|
≤
0.1 mA
V
DD
Q
– 0.2
–
V
DD
Q
V
3, 4
V
OH
Note1
V
DD
Q/2–0.12
–
V
DD
Q/2+0.12
V
3, 4
Low level output voltage
V
OL(Low)
I
OL
≤
0.1 mA
V
SS
–
0.2
V
3, 4
V
OL
Note2
V
DD
Q/2–0.12
–
V
DD
Q/2+0.12
V
3, 4
Notes 1.
Outputs are impedance-controlled. | I
OH
| = (V
DD
Q/2)/(RQ/5) for values of 175
≤
RQ
≤
350
.
2.
Outputs are impedance-controlled. I
OL
= (V
DD
Q/2)/(RQ/5) for values of 175
≤
RQ
≤
350
.
3.
AC load current is higher than the shown DC values.
4.
HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Capacitance (T
A =
25
°
C, f = 1MHz)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
4
5
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
6
7
pF
Clock Input capacitance
C
clk
V
clk
= 0 V
5
6
pF
Remark
These parameters are periodically sampled and not 100% tested.
相關(guān)PDF資料
PDF描述
UPD44324362F5-E40-EQ2 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324082 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324092F5-E50-EQ2 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324182F5-E50-EQ2 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324084F5-E33-EQ2 36M-BIT DDRII SRAM 4-WORD BURST OPERAT
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