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參數(shù)資料
| 型號： | UPD44325094F5-E50-EQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| 中文描述： | 36M條位推出QDRII SRAM的4個字爆發(fā)運作 |
| 文件頁數(shù)： | 25/36頁 |
| 文件大小： | 377K |
| 代理商： | UPD44325094F5-E50-EQ2 |
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25
Preliminary Data Sheet
M16784EJ1V0DS
μ
PD44325084, 44325094, 44325184, 44325364
JTAG Instructions
Instructions
Description
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output drive is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is
placed in the test-logic-reset state.
BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed
between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This
allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD
SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-
DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to sample metastable input will not harm the device, repeatable results
cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (t
CS
plus t
CH
). The RAMs clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving
the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
IR1
IR0
Instruction
Note
0
0
0
EXTEST
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
0
1
1
RESERVED
1
0
0
SAMPLE / PRELOAD
1
0
1
RESERVED
1
1
0
RESERVED
1
1
1
BYPASS
Note 1.
TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44325084 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325364F5-E50-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325084F5-E33-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325184F5-E33-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325364F5-E33-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44325182BF5-E33-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD44325182BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
| UPD44325182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
| UPD44325184BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325184BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
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