參數(shù)資料
型號: UPD44325184F5-E33-EQ2
廠商: NEC Corp.
英文描述: 36M-BIT QDRII SRAM 4-WORD BURST OPERATION
中文描述: 36M條位推出QDRII SRAM的4個字爆發(fā)運作
文件頁數(shù): 3/36頁
文件大?。?/td> 377K
代理商: UPD44325184F5-E33-EQ2
3
Preliminary Data Sheet
M16784EJ1V0DS
μ
PD44325084, 44325094, 44325184, 44325364
Pin Configurations
/
×××
indicates active low signal.
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[
μ
PD44325084F5-EQ2]
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
V
SS
A
/W
/NW1
/K
NC
/R
A
A
CQ
B
NC
NC
NC
A
NC
K
/NW0
A
NC
NC
Q3
C
NC
NC
NC
V
SS
A
NC
A
V
SS
NC
NC
D3
D
NC
D4
NC
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
E
NC
NC
Q4
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
D2
Q2
F
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
G
NC
D5
Q5
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
H
/DLL
V
REF
V
DD
Q
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
V
DD
Q
V
REF
ZQ
J
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
Q1
D1
K
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
L
NC
Q6
D6
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
Q0
M
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
D0
N
NC
D7
NC
V
SS
A
A
A
V
SS
NC
NC
NC
P
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
/C
A
A
A
TMS
TDI
A
D0 to D7
Q0 to Q7
/R
/W
/NW0, /NW1
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
Refer to
Package Drawing
for the index mark.
2.
2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
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