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參數(shù)資料
| 型號(hào)： | UPD44325184F5-E40-EQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| 中文描述： | 36M條位推出QDRII SRAM的4個(gè)字爆發(fā)運(yùn)作 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 377K |
| 代理商： | UPD44325184F5-E40-EQ2 |
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10
Preliminary Data Sheet
M16784EJ1V0DS
μ
PD44325084, 44325094, 44325184, 44325364
Truth Table
Operation
CLK
/R
/W
D or Q
WRITE cycle
L
→
H
H
L
Data in
Load address, input write data on two
Input data
D
A
(A+0)
D
A
(A+1)
D
A
(A+2)
D
A
(A+3)
consecutive K and /K rising edge
Input clock
K(t+1)
↑
/K(t+1)
↑
K(t+2)
↑
/K(t+2)
↑
READ cycle
L
→
H
L
X
Data out
Load address, read data on two
Output data
Q
A
(A+0)
Q
A
(A+1)
Q
A
(A+2)
Q
A
(A+3)
consecutive C and /C rising edge
Output clock
/C(t+1)
↑
C(t+2)
↑
/C(t+2)
↑
C(t+3)
↑
NOP (No operation)
L
→
H
H
H
D=X or Q=High-Z
STANDBY(Clock stopped)
Stopped
X
X
Previous state
Remarks 1.
H : High level, L : Low level,
×
: don’t care,
↑
: rising edge.
2.
Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges
except if C and /C are HIGH then data outputs are delivered at K and /K rising edges.
3.
/R and /W must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at
the rising edge of K.
4.
This device contains circuitry that will ensure the outputs will be in high impedance during power-up.
5.
Refer to state diagram and timing diagrams for clarification.
6.
It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
7.
If /R was LOW to initiate the previous cycle, this signal becomes a don't care for this operation however it
is strongly recommended that this signal is brought HIGH as shown in the truth table.
8.
/W during write cycle and /R during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44325084F5-E50-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325184F5-E50-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325094F5-E40-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325094F5-E50-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325084 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44325362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325362F5-E40-EQ2 | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44325364BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325364BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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