參數(shù)資料
型號： UPD44325364F5-E33-EQ2
廠商： NEC Corp.
英文描述： 36M-BIT QDRII SRAM 4-WORD BURST OPERATION
中文描述： 36M條位推出QDRII SRAM的4個字爆發(fā)運作
文件頁數(shù)： 9/36頁
文件大?。?/td> 377K
代理商： UPD44325364F5-E33-EQ2
9
Preliminary Data Sheet
M16784EJ1V0DS
μ
PD44325084, 44325094, 44325184, 44325364
[
μ
PD44325364]
DATA
REGISTRY
& LOGIC
O
R
/W
/BW0
/BW1
/BW2
/BW3
/R
K
/K
K
K
/R
/W
K
ADDRESS
18
18
D0 to D35
36
O
S
O
B
36
72
72
72
144
72
MUX
MUX
ADDRESS
REGISTRY
& LOGIC
2
MEMORY
ARRAY
18
x 144
W
D
S
A
W
R
Q0 to Q35
C, /C
OR
K, /K
CQ,
/CQ
2
Power-on Sequence
The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after
V
DD
/V
DD
Q stable and when starting the clock before V
DD
/V
DD
Q stable.
1. Clock starts after V
DD
/V
DD
Q stable
V
DD
/V
DD
Q
V
DD
/V
DD
Q Stable (<
±
0.1 V DC per 50 ns)
Clock Start
1,024 cycles or more
Stable Clock
Start
Normal Operation
Clock
2. Clock starts before V
DD
/V
DD
Q stable
V
DD
/V
DD
Q
V
DD
/V
DD
Q Stable (<
±
0.1 V DC per 50 ns)
Clock Start
1,024 cycles or more
Stable Clock
30 ns (MIN.)
DLL Reset or DLL Off
Start
Normal Operation
Clock
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