參數(shù)資料
型號(hào)： UPD4481161GF-A85
廠商： NEC Corp.
英文描述： 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
中文描述： 800萬(wàn)位ZEROSB SRAM的流動(dòng)經(jīng)手術(shù)
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 326K
代理商： UPD4481161GF-A85
10
Data Sheet M15561EJ3V0DS
μ
PD4481161, 4481181, 4481321, 4481361
State Diagram
DESELECT
BEGIN
READ
BURST
READ
BEGIN
WRITE
BURST
WRITE
WRITE
READ
READ
DS
DS
WRITE
READ
BURST
BURST
WRITE
READ
WRITE
READ
BURST
WRITE
BURST
DS
BURST
DS
DS
Command
Operation
DS
Deselect
Read
New Read
Write
New Write
Burst
Burst Read, Burst Write or Continue Deselect
Remarks 1.
States change on the rising edge of the clock.
2.
A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only
blocks the clock (CLK) input and does not change the state of the device.
相關(guān)PDF資料
PDF描述
UPD4481181GF-A85 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481321GF-A85 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481361GF-A85 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481161GF-C75 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481181GF-C75 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
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