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參數(shù)資料
| 型號(hào)： | UPD4481181GF-C75 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION |
| 中文描述： | 800萬位ZEROSB SRAM的流動(dòng)經(jīng)手術(shù) |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 326K |
| 代理商： | UPD4481181GF-C75 |
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14
Data Sheet M15561EJ3V0DS
μ
PD4481161, 4481181, 4481321, 4481361
DC Characteristics (V
DD
= 3.3 ± 0.165 V or 2.5 ± 0.125 V)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input leakage current
I
LI
V
IN
(except ZZ, MODE) = 0 V to V
DD
–2
+2
μ
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
DD
Q, Outputs are disabled.
–2
+2
μ
A
Operating supply current
I
DD
Device selected,
-A65
250
mA
Cycle = MAX.,
-A65Y
V
IN
≤
V
IL
or V
IN
≥
V
IH
,
-A75, -C75
225
I
I/O
= 0 mA
-A75Y, -C75Y
-A85, -C85
200
-A85Y, -C85Y
Standby supply current
I
SB
Device deselected, Cycle = 0 MHz,
30
mA
V
IN
≤
V
IL
or V
IN
≥
V
IH
, All inputs are static.
I
SB1
Device deselected, Cycle = 0 MHz,
15
V
IN
≤
0.2 V or V
IN
≥
V
DD
–
0.2 V,
V
I/O
≤
0.2 V, All inputs are static.
I
SB2
Device deselected, Cycle = MAX.,
110
V
IN
≤
V
IL
or V
IN
≥
V
IH
Power down supply current
I
SBZZ
ZZ
≥
V
DD
– 0.2 V, V
I/O
≤
V
DD
Q + 0.2 V
15
mA
2.5 V LVTTL Interface
High level output voltage
V
OH
I
OH
= –2.0 mA
1.7
V
I
OH
= –1.0 mA
2.1
Low level output voltage
V
OL
I
OL
= +2.0 mA
0.7
V
I
OL
= +1.0 mA
0.4
3.3 V LVTTL Interface
High level output voltage
V
OH
I
OH
= –4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Capacitance (T
A
= 25
°
C, f = 1MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6.0
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8.0
pF
Clock input capacitance
C
clk
V
clk
= 0 V
6.0
pF
Remark
These parameters are periodically sampled and not 100
%
tested.
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