參數(shù)資料
型號： UPD4481321GF-A85
廠商： NEC Corp.
英文描述： 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
中文描述： 800萬位ZEROSB SRAM的流動經(jīng)手術(shù)
文件頁數(shù)： 9/28頁
文件大?。?/td> 326K
代理商： UPD4481321GF-A85
9
Data Sheet M15561EJ3V0DS
μ
PD4481161, 4481181, 4481321, 4481361
μ
PD4481321,
μ
PD4481361]
A0 to A17
MODE
CLK
/CKE
ADV
/BW1
/BW2
/BW3
/BW4
/WE
/G
/CE
CE2
/CE2
Address
register 0
Burst
logic
Write address
register
Write registry and
data coherency
control logic
Write
drivers
D
ADV
K
A1
A1
’
A0
’
S
Read
logic
Input
register
E
O
E
I/O1 to I/O32
I/OP1 to I/OP4
18
16
18
18
18
32/36
32/36
32/36
32/36
ZZ
Power down control
K
Memory Cell Array
256 x 32 columns
(8,388,608 bits)
256 x 36 columns
(9,437,184 bits)
1,024 rows
μ
PD4481321,
μ
PD4481361]
nterleaved Burst Sequence Table (MODE = V
DD
)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
相關(guān)PDF資料
PDF描述
UPD4481361GF-A85 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481161GF-C75 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481181GF-C75 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481321GF-C75 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481161GF-A75 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
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