參數(shù)資料
型號： UPD4481321GF-C85
廠商： NEC Corp.
英文描述： 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
中文描述： 800萬位ZEROSB SRAM的流動經(jīng)手術(shù)
文件頁數(shù)： 1/28頁
文件大?。?/td> 326K
代理商： UPD4481321GF-C85
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD4481161, 4481181, 4481321, 4481361
8M-BIT ZEROSB
TM
SRAM
FLOW THROUGH OPERATION
Document No. M15561EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
DATA SHEET
The mark
shows major revised points.
2001
Description
The
μ
PD4481161 is a 524,288-word by 16-bit, the
μ
PD4481181 is a 524,288-word by 18-bit, the
μ
PD4481321 is a
262,144-word by 32-bit and the
μ
PD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD4481161,
μ
PD4481181,
μ
PD4481321 and
μ
PD4481361 are optimized to eliminate dead cycles for read to
write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The
μ
PD4481161,
μ
PD4481181,
μ
PD4481321 and
μ
PD4481361 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State
(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes
normal operation.
The
μ
PD4481161,
μ
PD4481181,
μ
PD4481321 and
μ
PD4481361 are packaged in 100-pin PLASTIC LQFP with a
1.4 mm package thickness for high density and low capacitive loading.
Features
Low voltage core supply : V
DD
= 3.3 ± 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y)
V
DD
= 2.5 ± 0.125 V (-C75, -C85, -C75Y, -C85Y)
Synchronous operation
Operating temperature : T
A
= 0 to 70
°
C (-A65, -A75, -A85, -C75, -C85)
T
A
=
40 to
+
85
°
C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)
100 percent bus utilization
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for flow through operation
All registers triggered off positive clock edge
3.3V or 2.5V LVTTL Compatible : All inputs and outputs
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4 (
μ
PD4481321 and
μ
PD4481361)
/BW1 and /BW2 (
μ
PD4481161 and
μ
PD4481181)
Three chip enables for easy depth expansion
Common I/O using three state outputs
相關(guān)PDF資料
PDF描述
UPD4481161GF-A65 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481181GF-A65 POT 50 OHM 3/8 SQ CERM SL ST
UPD4481321GF-A65 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481361GF-A65 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481361GF-C75 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
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