參數(shù)資料
型號(hào)： UPD4481361GF-C75
廠商： NEC Corp.
英文描述： 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
中文描述： 800萬位ZEROSB SRAM的流動(dòng)經(jīng)手術(shù)
文件頁數(shù)： 11/28頁
文件大?。?/td> 326K
代理商： UPD4481361GF-C75
11
Data Sheet M15561EJ3V0DS
μ
PD4481161, 4481181, 4481321, 4481361
Asynchronous Truth Table
Operation
/G
I/O
Read Cycle
L
Dout
Read Cycle
H
High-Z
Write Cycle
×
High-Z, Din
Deselected
×
High-Z
Remark
×
: don’t care
Synchronous Truth Table
Operation
/CE
CE2
/CE2
ADV
/WE
/BWs
/CKE
CLK
I/O
Address
Note
Deselected
H
×
×
L
×
×
L
L
→
H
High-Z
None
1
Deselected
×
L
×
L
×
×
L
L
→
H
High-Z
None
1
Deselected
×
×
H
L
×
×
L
L
→
H
High-Z
None
1
Continue Deselected
×
×
×
H
×
×
L
L
→
H
High-Z
None
1
Read Cycle / Begin Burst
L
H
L
L
H
×
L
L
→
H
Dout
External
Read Cycle / Continue Burst
×
×
×
H
×
×
L
L
→
H
Dout
Next
Write Cycle / Begin Burst
L
H
L
L
L
L
L
L
→
H
Din
External
Write Cycle / Continue Burst
×
×
×
H
×
L
L
L
→
H
Din
Next
Write Cycle / Write Abort
L
H
L
L
L
H
L
L
→
H
High-Z
External
Write Cycle / Write Abort
×
×
×
H
×
H
L
L
→
H
High-Z
Next
Stall / Ignore Clock Edge
×
×
×
×
×
×
H
L
→
H
Current
2
Notes
1.
Deselect status is held until new “Begin Burst” entry.
2.
If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low
impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will
be performed during the Ignore Clock Edge cycle.
Remarks 1.
×
: don’t care
2.
/BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.
/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.
相關(guān)PDF資料
PDF描述
UPD4481181GF-C85 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481161 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481161GF-C85 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481361 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
UPD4481361GF-C85 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
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