參數(shù)資料
型號: UPD4482162GF-C60Y
廠商: NEC Corp.
英文描述: 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
中文描述: 800萬位CMOS同步快速靜態(tài)存儲器流水線操作單周期取消選擇
文件頁數(shù): 7/28頁
文件大?。?/td> 445K
代理商: UPD4482162GF-C60Y
7
Data Sheet M14522EJ3V0DS
μ
PD4482162, 4482182, 4482322, 4482362
Block Diagrams
[
μ
PD4482162,
μ
PD4482182]
Address
Registers
Binary
Counter
and Logic
CLR
Q0
Q1
Byte 1
Write Register
Byte 1
Write Driver
8/9
Byte 2
Write Register
Byte 2
Write Driver
8/9
Enable
Register
Row and Column
Decoders
Memory cell array
1,024 rows
512
×
16 columns
(8,388,608 bits)
512
×
18 columns
(9,437,184 bits)
Output
Registers
Output
Buffers
Input
Registers
16/18
17
19
A0, A1
A1’
A0’
16/18
2
16/18
A0 to A18
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O16
I/OP1 to I/OP2
Enable Delay
Register
ZZ
Power Down Control
19
Burst Sequence
[
μ
PD4482162,
μ
PD4482182]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A18 to A2, A1, A0
1st Burst Address
A18 to A2, A1, /A0
2nd Burst Address
A18 to A2, /A1, A0
3rd Burst Address
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
1st Burst Address
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
2nd Burst Address
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
3rd Burst Address
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
相關PDF資料
PDF描述
UPD4482182 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
UPD4482162GF-A44 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
UPD4482182GF-A44 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
UPD4482162GF-A44Y 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
UPD4482182GF-A44Y 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
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