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參數(shù)資料
| 型號： | UPD45128163G5-A80-9JF |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 128兆位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 35/92頁 |
| 文件大小： | 1107K |
| 代理商： | UPD45128163G5-A80-9JF |
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Data Sheet M12650EJBV0DS00
35
μ
PD45128441, 45128841, 45128163
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
/CAS
Grade
Maximum
×
8
Unit
Notes
latency
×
4
×
16
Operating current
I
CC1
Burst length = 1,
t
RC
≥
t
RC (MIN.)
, Io = 0 mA,
One bank active
CL = 2
-A75
100
100
110
mA
1
-A80
100
100
110
-A10
100
100
110
-A10B
90
100
110
CL = 3
-A75
105
105
115
-A80
100
100
110
-A10
100
100
110
-A10B
95
100
110
Precharge standby current
I
CC2
P
CKE
≤
V
IL (MAX.)
, t
CK
= 15 ns
CKE
≤
V
IL (MAX.)
, t
CK
=
∞
CKE
≥
V
IH (MIN.)
, t
CK
= 15 ns, /CS
≥
V
IH (MIN.)
,
Input signals are changed one time during 30 ns.
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
,
Input signals are stable.
CKE
≤
V
IL (MAX.)
, t
CK
= 15 ns
CKE
≤
V
IL (MAX.)
, t
CK
=
∞
CKE
≥
V
IH (MIN.)
, t
CK
= 15 ns, /CS
≥
V
IH (MIN.)
,
Input signals are changed one time during 30 ns.
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
,
Input signals are stable.
t
CK
≥
t
CK (MIN.)
, Io = 0 mA,
All banks active
1
1
1
mA
in power down mode
I
CC2
PS
1
1
1
Precharge standby current
in non power down mode
I
CC2
N
20
20
20
mA
I
CC2
NS
8
8
8
Active standby current
I
CC3
P
5
5
5
mA
in power down mode
I
CC3
PS
4
4
4
Active standby current
in non power down mode
I
CC3
N
30
30
30
mA
I
CC3
NS
20
20
20
Operating current
I
CC4
CL = 2
-A75
105
120
145
mA
2
(Burst mode)
-A80
105
120
145
-A10
85
95
110
-A10B
75
85
100
CL = 3
-A75
140
155
185
-A80
130
145
175
-A10
110
125
140
-A10B
110
125
140
CBR (auto) refresh current
I
CC5
t
RC
≥
t
RC (MIN.)
CL = 2
-A75
230
230
230
mA
3
-A80
230
230
230
-A10
230
230
230
-A10B
220
220
220
CL = 3
-A75
240
240
240
-A80
230
230
230
-A10
230
230
230
-A10B
220
220
220
Self refresh current
I
CC6
CKE
≤
0.2 V
2
2
2
mA
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured condition that addresses are changed only one time during t
CK (MIN.)
.
2.
I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured condition that addresses are changed only one time during t
CK (MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
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