參數(shù)資料
型號： UPD45128163G5-A80L-9JF
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述： 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： PLASTIC, TSOP2-54
文件頁數(shù)： 35/92頁
文件大?。?/td> 682K
代理商： UPD45128163G5-A80L-9JF
Data Sheet E0031N30
35
μ
PD45128441, 45128841, 45128163
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
/CAS Grade
Maximum
×
8
Unit
Notes
latency
×
4
×
16
Operating current
I
CC1
Burst length = 1,
t
RC
≥
t
RC (MIN.)
, Io = 0 mA,
One bank active
CL = 2 -A75A
110
110
120
mA
1
-A75
100
100
110
-A80
100
100
110
-A10
100
100
110
CL = 3 -A75A
110
110
120
-A75
105
105
115
-A80
100
100
110
CKE
≤
V
IL (MAX.)
, t
CK
= 15 ns
I
CC2
PS CKE
≤
V
IL (MAX.)
, t
CK
=
∞
I
CC2
N
Input signals are changed one time during 30 ns.
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
,
Input signals are stable.
CKE
≤
V
IL (MAX.)
, t
CK
= 15 ns
I
CC3
PS CKE
≤
V
IL (MAX.)
, t
CK
=
∞
I
CC3
N
Input signals are changed one time during 30 ns.
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
,
Input signals are stable.
t
CK
≥
t
CK (MIN.)
, Io = 0 mA,
All banks active
-A10
100
100
110
Precharge standby current
I
CC2
P
1
1
1
mA
in power down mode
1
1
1
Precharge standby current
in non power down mode
CKE
≥
V
IH (MIN.)
, t
CK
= 15 ns, /CS
≥
V
IH (MIN.)
,
20
20
20
mA
I
CC2
NS
8
8
8
Active standby current
I
CC3
P
5
5
5
mA
in power down mode
4
4
4
Active standby current
in non power down mode
CKE
≥
V
IH (MIN.)
, t
CK
= 15 ns, /CS
≥
V
IH (MIN.)
,
30
30
30
mA
I
CC3
NS
20
20
20
Operating current
I
CC4
CL = 2 -A75A
140
155
185
mA
2
(Burst mode)
-A75
105
120
145
-A80
105
120
145
-A10
85
95
110
CL = 3 -A75A
140
155
185
-A75
140
155
185
-A80
130
145
175
-A10
110
125
140
CBR (auto) refresh current
I
CC5
t
RC
≥
t
RC (MIN.)
CL = 2 -A75A
270
270
270
mA
3
-A75
230
230
230
-A80
230
230
230
-A10
230
230
230
CL = 3 -A75A
270
270
270
-A75
240
240
240
-A80
230
230
230
CKE
≤
0.2 V
-A10
230
230
230
Self refresh current
I
CC6
-**
2
2
2
mA
-**L
0.8
0.8
0.8
mA
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured condition that addresses are changed only one time during t
CK (MIN.)
.
2.
I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured condition that addresses are changed only one time during t
CK (MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
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