參數(shù)資料
型號(hào)： UPD45128441G5-A10
廠商： NEC Corp.
英文描述： 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述： 128兆位同步DRAM 4銀行，LVTTL
文件頁(yè)數(shù)： 91/92頁(yè)
文件大小： 1107K
代理商： UPD45128441G5-A10
Data Sheet M12650EJBV0DS00
91
μ
PD45128441, 45128841, 45128163
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
相關(guān)PDF資料
PDF描述
UPD45128841G5-A10 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128441G5-A10-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128841G5-A10-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128163 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128163G5-A80-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
相關(guān)代理商/技術(shù)參數(shù)
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UPD4528C 制造商:Panasonic Industrial Company 功能描述:IC SUB:TC4528BP OR TVSTC4528BP
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