- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384043 > UPD45128841G5-A75L-9JF (ELPIDA MEMORY INC) 128M-bit Synchronous DRAM 4-bank, LVTTL PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD45128841G5-A75L-9JF |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 25/92頁 |
| 文件大?。?/td> | 682K |
| 代理商： | UPD45128841G5-A75L-9JF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Data Sheet E0031N30
25
μ
PD45128441, 45128841, 45128163
9. Precharge
The precharge command can be issued anytime after t
RAS (MIN.)
is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after t
RP
is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
It is depending on the /CAS latency and clock cycle time.
T0
T1
T2
T3
T4
T5
T6
T7
Burst length=4
READ
READ
Q1
Q2
Q3
Q4
PRE
Hi-Z
Q1
Q2
Q3
Q4
PRE
Hi-Z
(t
RAS
must be satisfied)
CLK
Command
/CAS latency = 2
DQ
Command
/CAS latency = 3
DQ
T8
In order to write all data to the memory cell correctly, the asynchronous parameter “t
DPL
” must be satisfied. The t
DPL
(MIN.)
specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing t
DPL (MIN.)
with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency
Read
Write
2
–1
+t
DPL (MIN.)
3
–2
+t
DPL (MIN.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD45128841G5-A80-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128841G5-A80L-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128441G5-A75L-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128163G5-A75-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128163G5-A75A-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4516161AG5A109NF | 制造商:NEC Electronics Corporation 功能描述: |
| UPD4516161AG5-A10-9NF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| UPD4528BC | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD4528C | 制造商:Panasonic Industrial Company 功能描述:IC SUB:TC4528BP OR TVSTC4528BP |
| UPD4564163G5-A10B-9JF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 4M x 16, 54 Pin, Plastic, TSOP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。