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參數(shù)資料
| 型號： | UPD4702G |
| 廠商： | NEC Corp. |
| 元件分類： | 通用總線功能 |
| 英文描述： | INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS |
| 中文描述： | 增量式編碼器8位加/減計(jì)數(shù)器CMOS集成電路 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 167K |
| 代理商： | UPD4702G |
5
μ
PD4702
2.
OPERATING PRECAUTIONS
As the
μ
PD4702 incorporates an 8-bit counter, a large transient current flows in the case of a count value which
changes all the bits (such as 00
H
0FF
H
or 7F
H
080
H
). This will cause misoperation unless the impedance of the
power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1
μ
F)
be connected between V
DD
and V
SS
right next to the IC as shown in Fig. 3.
Fig. 3 Decoupling Capacitor
V
DD
V
SS
+5 V
C
C : 0.1
μ
F tantalum electrolytic laminated
ceramic capacitor, etc.
Also, if a pulse shorter than the phase difference time t
SAB
(70 ns) is input to the A/ B phase inputs, this will result
in a miscount. Therefore, if this kind of pulse is to be input because of encoder bounds, etc., a filter should be inserted
in the A & B phase inputs.
Fig. 4 A & B Phase Input Pulses
A Phase (or B Phase)
B Phase (or A Phase)
PW
If a pulse such that PW < 70 ns is input
in the A or B phase, there is a danger of
a miscount.
If PW is at 70 ns or more, the count value remains the same before and after pulse input. (UP count
→
DOWN
count or DOWN count
→
UP count is implemented, and therefore the the result is no change in the count value.)
μ
PD4702
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