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參數(shù)資料
| 型號(hào)： | UPD4724GS-GJG |
| 廠商： | NEC Corp. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C |
| 中文描述： | 電可擦除可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 140K |
| 代理商： | UPD4724GS-GJG |
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2
μ
PD4724
BLOCK DIAGRAM/PIN CONFIGURATION (TOP VIEW)
C
1+
V
DD
V
CC
C
1–
C
5+
GND
C
4+
GND
C
4–
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
C
3
+10 V
C
1
C
5
+3.3 V
or
+5 V
D
IN1
D
IN2
D
IN3
R
OUT1
R
OUT2
R
OUT3
R
OUT4
R
OUT5
D
OUT1
D
OUT2
D
OUT3
R
IN1
R
IN2
R
IN3
R
IN4
R
IN5
Note
EN
V
CHA
STBY
–10 V
C
2
C
4
300
300
300
5.5 k
5.5 k
5.5 k
5.5 k
5.5 k
+
+
+
+
+
C
5–
Note
The pull-up resistors of the driver inputs are active resistors.
Remark 1.
V
DD
and V
SS
are pins that output the voltage boosted internally. Don't connect these pins to the
load.
2.
Capacitors with a breakdown voltage of 20 V or higher are recommended for C
1
to C
5
. And it is
recommended to insert the capacitor that is 0.1
μ
F to 1
μ
F between V
CC
and GND.
3.
The capacitor C
5
does not have to be connected when the IC is used in 5 V mode (V
CHA
= L).
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