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參數(shù)資料
| 型號： | UPD6105C002 |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 252K |
| 代理商： | UPD6105C002 |
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μ
PD61P24
20
17.3 Program Memory Reading Procedure
(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low.
(2) Supply 5 V to the V
DD
pin. Keep the V
PP
pin low.
(3) Wait for 10
μ
s, and supply 5 V to the V
PP
pin.
(4) Set the mode in which the program memory address is cleared to 0, by using the mode setting pins.
(5) Supply 6 V to V
DD
and 12.5 V to V
PP
.
(6) Set the program inhibit mode.
(7) Set the verify mode. If a clock pulse is input to the CLK pin, the data of one address is output each time the
pulse has been input to the CLK pin four times.
(8) Set the program inhibit mode.
(9) Set the mode in which the program memory address is cleared to 0.
(10) Change the voltage on the V
DD
and V
PP
pins to 5 V.
(11) Turn off power supply.
Program memory reading steps (2) through (9) are illustrated below.
Hi-Z
Hi-Z
“ L ”
MD3
MD2
MD1
MD0
D0-D7
CLK
GND
V
DD
V
DD
V
PP
V
PP
V
DD
GND
V
DD
+1
Reset
Data output
Data output
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