- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378739 > UPD65052-QFP80P.55SQ ASIC PDF資料下載
參數(shù)資料
| 型號： | UPD65052-QFP80P.55SQ |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 24/64頁 |
| 文件大?。?/td> | 399K |
| 代理商： | UPD65052-QFP80P.55SQ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
24
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
Table 5-3. Standby Mode Setup (HALT #b
3
b
2
b
1
b
0
B) and Release Conditions
Operand Value of
HALT Instruction
Setting Mode
Precondition for Setup
Release Condition
b
3
b
2
b
1
b
0
0
0
0
0
STOP
All K
I/O
pins are high-level output.
High level is input to at least one
of K
I
pins.
0
1
1
STOP
All K
I/O
pins are high-level output.
High level is input to at least one
of K
I
pins.
1
1
0
STOP
Note 1
The K
I/O0
pin is high-level output.
High level is input to at least one
of K
I
pins.
1
Any of the
STOP
[The following condition is added in addition to the above.]
combinations of
—
High level is input to at least one
b
2
b
1
b
0
above
of S
0
, S
1
and S
2
pins
Note 2
.
0/1
1
0
1
HALT
—
When the timer’s down counter is 0
Notes 1.
When setting HALT #
×
110B, configure a key matrix by using the K
I/O0
pin and the K
I
pin so that an
internal reset takes effect at the time of program hang-up.
2.
At least one of the S
0
, S
1
and S
2
pins (the pin used for releasing the standby) must be specified as
follows:
S
0
, S
1
pins : INPUT mode (specified by bits 0 and 2 of the P4 register)
S
2
pin
: Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer
output permit flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
相關PDF資料 |
PDF描述 |
|---|---|
| UPD65052-QFP80P.7X.9 | ASIC |
| UPD6529C | Consumer IC |
| UPD65301 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65343 | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| UPD65344 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UPD65060 | 制造商:NEC 制造商全稱:NEC 功能描述:UPD65000 (CMOS-3) SERIES 2-MICRON CMOS GATE ARRAYS |
| UPD65080 | 制造商:NEC 制造商全稱:NEC 功能描述:UPD65000 (CMOS-3) SERIES 2-MICRON CMOS GATE ARRAYS |
| UPD65100 | 制造商:NEC 制造商全稱:NEC 功能描述:UPD65000 (CMOS-3) SERIES 2-MICRON CMOS GATE ARRAYS |
| UPD6529C | 制造商:NEC 制造商全稱:NEC 功能描述:AUTOMOTIVE CLOCK CMOS LSI |
| UPD652C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。