- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378740 > UPD65365 CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] PDF資料下載
參數(shù)資料
| 型號： | UPD65365 |
| 英文描述： | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設計手冊[05/2003] |
| 文件頁數(shù)： | 12/64頁 |
| 文件大小： | 399K |
| 代理商： | UPD65365 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
12
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple
manipulations with priority given to logical operations.
2.9 Flags
2.9.1 Status flag (F)
Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.
The status flag is set (to 1) in the following cases.
If the condition specified with the operand is met when the STTS instruction has been executed
When STANDBY mode is released.
When the release condition is met at the point of executing the HALT instruction. (In this case, the system
is not placed in STANDBY mode.)
Conversely, the status flag is cleared (to 0) in the following cases:
If the condition specified with the operand is not met when the STTS instruction has been executed.
When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met
at the point of executing the HALT instruction. (In this case, the system is not placed in STANDBY mode.)
Table 2-1. Conditions for Status Flag (F) To Be Set by STTS Instruction
Operand Value of STTS Instruction
Condition for Status Flag (F) To Be Set
b
3
b
2
b
1
b
0
0
0
0
0
High level is input to at least one of K
I
pins.
0
1
1
High level is input to at least one of K
I
pins.
1
1
0
High level is input to at least one of K
I
pins.
1
0
1
The down counter of the timer is 0.
1
Either of the combinations
of b
2
, b
1
, and b
0
above.
[The following condition is added in addition to the above.]
High level is input to at least one of S
0
, S
1
, and S
2
Note
pins.
Note
The use of STOP mode release for the S
2
pin must be enabled (bit 3 of P4 register is set to 1.)
相關PDF資料 |
PDF描述 |
|---|---|
| UPD65366 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65367 | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| UPD65368 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65369 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65451 | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UPD65366 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65367 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| UPD65368 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65369 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65370 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
發(fā)布緊急采購，3分鐘左右您將得到回復。