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參數(shù)資料
| 型號： | UPD65567 |
| 英文描述： | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設計手冊[05/2003] |
| 文件頁數(shù)： | 15/64頁 |
| 文件大小： | 399K |
| 代理商： | UPD65567 |
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15
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
3.1 K
I/O
Port (P0)
The K
I/O
port is an 8-bit input/output port for key scan output.
INPUT/OUTPUT mode is set by bit 1 of the P4 register.
If a read instruction is executed, the pin state can be read in INPUT mode, whereas the output latch contents
can be read in OUTPUT mode.
If the write instruction is executed, data can be written to the output latch regardless of INPUT or OUTPUT mode.
When reset, the port is placed in OUTPUT mode; and the value of the output latch (P0) becomes 1111 1111B.
The K
I/O
port contains the pull-down resistor, allowing pull-down in INPUT mode only.
Caution During double pressing of a key, a high-level output and a low-level output may coincide with
each other at the K
I/O
port. To avoid this, the low-level output current of the K
I/O
port is held
low. Therefore, be careful when using the K
I/O
port for purposes other than key scan output.
The K
I/O
port is so designed that, even when connected directly to V
DD
within the normal supply
voltage range (V
DD
= 2.0 to 3.6 V), no problem may occur.
Table 3-2. K
I/O
Port (P0)
Bit
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Name
K
I/O7
K
I/O6
K
I/O5
K
I/O4
K
I/O3
K
I/O2
K
I/O1
K
I/O0
b
0
-b
7
: In reading : In INPUT mode, the K
I/O
pin’s state is read.
In OUTPUT mode, the K
I/O
pin’s output latch contents are read.
In writing
: Data is written to the K
I/O
pin’s output latch regardless of INPUT or OUTPUT mode.
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