參數(shù)資料
型號(hào): UPD70208HGF-20-3B9
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁(yè)數(shù): 79/110頁(yè)
文件大?。?/td> 625K
代理商: UPD70208HGF-20-3B9
79
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
TOUT1
↓→
T
X
D delay time
TCTL2 setup time (vs. CLKOUT
)
TCTL2 setup time (vs. TCLK
)
TCTL2 hold time (vs. CLKOUT
)
TCTL2 hold time (vs. TCLK
)
TCTL2 high-level width
TCTL2 low-level width
TOUT output delay time (vs. CLKOUT
)
TOUT output delay time (vs. TCLK
)
TOUT output delay time (vs. TCTL2
)
TCLK rise time
TCLK fall time
TCLK high-level width
TCLK low-level width
TCLK cycle
Access interval
Note 1
REFRQ
delay time (vs. MRD
)
Note 2
RESET pulse width
Note 3
(1)
μ
PD70208H, 70216H-10/12/16 (T
A
= –40 to +85
°
C, V
DD
= 3 V
±
10%) (3/3)
Output Pin Load Capacitance: C
L
= 100 pF
μ
PD70208H-10
μ
PD70216H-10
Unit
Parameter
μ
PD70208H-12
μ
PD70216H-12
t
DTX
500
500
500
ns
t
SGK
50
50
50
ns
t
SGTK
50
50
50
ns
t
HKG
100
100
100
ns
t
HTKG
50
50
50
ns
t
GGH
50
50
50
ns
t
GGL
50
50
50
ns
t
DKTO
200
200
200
ns
t
DTKTO
150
150
150
ns
t
DGTO
120
120
120
ns
t
TKR
25
25
25
ns
t
TKF
25
25
25
ns
t
TKTKH
60
55
50
ns
t
TKTKL
60
55
50
ns
t
CYTK
200
DC
166
DC
125
DC
ns
t
AI
2t
CYK
–70
2t
CYK
–60
2t
CYK
–50
ns
t
DRQHRH
t
KKL
–50
t
KKL
–40
t
KKL
–30
ns
t
WRESL
4t
CYK
4t
CYK
4t
CYK
ns
Symbol
μ
PD70208H-16
μ
PD70216H-16
Notes 1.
Specification to guarantee read/write recovery time for I/O device.
2.
Specification to guarantee that REFRQ
is always later than MRD
.
Only guaranteed when the EREF bit of the SCTL register is 0.
3.
When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation
stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending
on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the
resonator and oscillator actually used.
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