
Data Sheet U14526EJ2V0DS00
18
μ
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25°C, V
SS
= 0 V)
Parameter
Symbol
Conditions
Ratings
Unit
V
DD
–0.5 to +4.6
V
AV
DD
–0.5 to +4.6
V
BV
DD
–0.5 to +4.6
V
AV
SS
–0.5 to +0.5
V
Supply voltage
BV
SS
–0.5 to +0.5
V
V
I1
Note 1
–0.5 to V
DD
+ 0.5
Note 4
V
Input voltage
V
I2
Note 2
–0.5 to BV
DD
+ 0.5
Note 4
V
Clock input voltage
V
K
X1, XT1, V
DD
= 2.7 to 3.6 V
–0.5 to V
DD
+ 1.0
Note 4
V
Analog input voltage
V
IAN
Note 3
(AV
DD
)
–0.5 to AV
DD
+ 0.5
Note 4
V
Analog reference input voltage
AV
REF
AV
REF
–0.5 to AV
DD
+ 0.5
Note 4
V
Per pin
4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
25
mA
Output current, low
I
OL
Total for P50 to P57, P60 to P65
25
mA
Per pin
–4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
–25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
–25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
–25
mA
Output current, high
I
OH
Total for P50 to P57, P60 to P65
–25
mA
V
O1
Note 1
, V
DD
= 2.7 to 3.6 V
–0.5 to V
DD
+ 0.5
Note 4
V
Output voltage
V
O2
Note 2
, BV
DD
= 2.7 to 3.6 V
–0.5 to BV
DD
+ 0.5
Note 4
V
Operating ambient temperature
T
A
–40 to +85
°
C
Storage temperature
T
stg
–65 to +150
°
C
Notes 1.
Ports 0, 1, 2, 3, 10, 11, 12, RESET, and their alternate-function pins.
2.
Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins.
3.
Ports 7, 8, and their alternate-function pins.
4.
Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions
1. Do not directly connect the output (or I/O) pins of IC products to each other, or to V
DD
, V
CC
,
and GND. Open-drain pins or open-collector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.