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參數(shù)資料
| 型號： | UPD703015AGC |
| 廠商： | NEC Corp. |
| 英文描述： | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | V850/SA1TM 32-/16-BIT單片機(jī) |
| 文件頁數(shù)： | 40/48頁 |
| 文件大小： | 309K |
| 代理商： | UPD703015AGC |
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Data Sheet U14526EJ2V0DS00
40
μ
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
I
2
C Bus Mode (
μ
PD703014AY, 703015AY, 703017AY only)
(T
A
= –40 to +85°C, V
DD
= 2.7 to 3.6 V, V
SS
= 0 V)
Normal Mode
High-Speed Mode
Parameter
Symbol
MIN.
MAX.
MIN.
MAX.
Unit
SCL clock frequency
f
CLK
0
100
0
400
kHz
Bus-free time (between
stop/start conditions)
t
BUF
<70>
4.7
–
1.3
–
μ
s
Hold time
Note 1
t
HD:STA
<71>
4.0
–
0.6
–
μ
s
SCL clock low-level width
t
LOW
<72>
4.7
–
1.3
–
μ
s
SCL clock high-level width
t
HIGH
<73>
4.0
–
0.6
–
μ
s
Setup time for start/restart
conditions
t
SU:STA
<74>
4.7
–
0.6
–
μ
s
CBUS
compatible
master
5.0
–
–
–
μ
s
Data hold
time
I
2
C mode
t
HD:DAT
<75>
0
Note 2
–
0
Note 2
0.9
Note 3
μ
s
Data setup time
t
SU:DAT
<76>
250
–
100
Note 4
–
ns
SDA and SCL signal rise
time
t
R
<77>
–
1000
20 + 0.1Cb
Note 5
300
ns
SDA and SCL signal fall
time
t
F
<78>
–
300
20 + 0.1Cb
Note 5
300
ns
Stop condition setup time
t
SU:STO
<79>
4.0
–
0.6
–
μ
s
Capacitance load of each
bus line
Cb
–
400
–
400
pF
Notes 1.
At the start condition, the first clock pulse is generated after the hold time.
2.
The system requires a minimum of 300 ns hold time internally for the SDA signal (at V
IHmin.
.
of SCL
signal) in order to occupy the undefined area at the falling edge of SCL.
3.
If the system does not extend the SCL signal low hold time (t
LOW
), only the maximum data hold time (t
HD
:
DAT
) needs to be satisfied.
4.
The high-speed mode I
high-speed mode I
If the system does not extend the SCL signal's low state hold time:
t
SU
:
DAT
≥
250 ns
If the system extends the SCL signal's low state hold time:
Transmit the following data bit to the SDA line prior to the SCL line release (t
Rmax.
+ t
SU
:
DAT
= 1000 +
250 = 1250 ns: Normal mode I
5.
Cb: Total capacitance of one bus line (unit: pF)
2
C bus can be used in the normal-mode I
2
C bus system. In this case, set the
2
C bus so that it meets the following conditions.
2
C bus specification).
Remark
The maximum operating frequency of the
μ
PD703014AY, 703015AY, and 703017AY is 17 MHz.
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|---|---|
| UPD703014A | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703014AF1 | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703014AGC | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703014AY | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703015A | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD703015AY | 制造商:NEC 制造商全稱:NEC 功能描述:V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703015AYF1 | 制造商:NEC 制造商全稱:NEC 功能描述:V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703015AYF1-XXX-EA6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|32-BIT|V850 CPU|CMOS|BGA|121PIN|PLASTIC |
| UPD703015AYGC | 制造商:NEC 制造商全稱:NEC 功能描述:V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703015B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:V850 Family(TM) for Architecture | User＇s Manual[03/2001] |
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