參數(shù)資料
型號: UPD703100GJ-40-8EU
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 106/132頁
文件大小: 1174K
代理商: UPD703100GJ-40-8EU
Preliminary Data Sheet U14168EJ2V0DS00
106
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(f) Write timing (EDO DRAM) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Row address setup time
<56>
t
ASR
(0.5 + w
RP
) T – 10
ns
Row address hold time
<57>
t
RAH
(0.5 + w
RH
) T – 10
ns
Column address setup time
<58>
t
ASC
0.5T – 10
ns
Column address hold time
<59>
t
CAH
(0.5 + w
DA
) T – 10
ns
RAS precharge time
<61>
t
RP
(0.5 + w
RP
) T – 5
ns
RAS hold time
<63>
t
RSH
(1.5 + w
DA
) T – 10
ns
Column address read time
(from RAS
)
<64>
t
RAL
(2 + w
CP
+ w
DA
) T – 10
ns
CAS-RAS precharge time
<66>
t
CRP
(1 + w
RP
) T – 10
ns
CAS hold time
<67>
t
CSH
(1.5 + w
RH
+ w
DA
)
T –
10
ns
Column address delay time from RAS
<76>
t
RAD
(0.5 + w
RH
) T – 10
ns
RAS-CAS delay time
<77>
t
RCD
(1 + w
RH
) T – 10
ns
CAS precharge time
<81>
t
CP
(0.5 + w
CP
) T – 5
ns
RAS hold time for CAS precharge
<83>
t
RHCP
(2 + w
CP
+ w
DA
) T – 10
ns
WE hold time (from CAS
)
<85>
t
WCH
(1 + w
DA
) T – 10
ns
Data hold time (from CAS
)
<87>
t
DH
(0.5 + w
DA
) T – 10
ns
WE read time
(from RAS
)
On-page
<88>
t
RWL
w
CP
= 0
(1.5 + w
DA
) T – 10
ns
WE read time
(from CAS
)
On-page
<89>
t
CWL
w
CP
= 0
(0.5 + w
DA
) T – 10
ns
WE pulse width
On-page
<92>
t
WP
w
CP
= 0
(1 + w
DA
) T – 10
ns
Write cycle time
<93>
t
HPC
(1 + w
DA
+ w
CP
) T – 10
ns
RAS pulse width
<94>
t
RASP
(2.5 + w
RH
+ w
DA
)
T –
10
ns
CAS pulse width
<95>
t
HCAS
(0.5 + w
DA
) T – 10
ns
Off-page
<101>
t
WCS1
(1 + w
RP
+ w
RH
)
T –
10
ns
WE setup time
(to CAS
)
On-page
<102>
t
WCS2
w
CP
1
w
CP
T – 10
ns
Off-page
<103>
t
DS1
(1.5 + w
RP
+ w
RH
)
T –
10
ns
Data setup time
(to CAS
)
On-page
<104>
t
DS2
(0.5 + w
CP
) T – 10
ns
Remarks 1.
T = t
CYK
2.
w
RP
: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
w
RH
: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
w
DA
: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5.
w
CP
: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
相關(guān)PDF資料
PDF描述
UPD703100-33 V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703100-40 V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
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