參數(shù)資料
型號(hào)： UPD70F3107AGJ-UEN
廠商： NEC Corp.
英文描述： 32-Bit Single-Chip Microcontrollers
中文描述： 32位單芯片微控制器
文件頁(yè)數(shù)： 43/99頁(yè)
文件大?。?/td> 528K
代理商： UPD70F3107AGJ-UEN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
43
The correspondence between the output address signals when the main memory (SDRAM) is accessed and the
PCI bus address signals is shown below.
Table 3-1. Row Address Output
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
(O_SD_ADR1 to O_SD_ADR25)
COLUMN_SIZE
Field Setting Value
25 to 18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
00 (8 bits)
25 to 18
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
01 (9 bits)
25 to 18
17
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
10 (10 bits)
25 to 18
17
16
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
11 (11 bits)
25 to 18
17
16
15
25
24
23
22
21
20
19
18
17
16
15
14
13
12
Table 3-2. Column Address Output (Precharge Command)
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
(O_SD_ADR1 to O_SD_ADR25)
BUS_SIZE
Bit Setting Value
25 to 18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (16 bits)
25 to 18
17
16
15
14
12
11
H
10
9
8
7
6
5
4
3
2
1
1 (32 bits)
25 to 18
17
16
15
14
12
H
11
10
9
8
7
6
5
4
3
2
1
Remark
H: High level
Table 3-3. Column Address Output (Read/Write Command)
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
(O_SD_ADR1 to O_SD_ADR25)
BUS_SIZE
Bit Setting Value
25 to 18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (16 bits)
25 to 18
17
16
15
14
12
11
L
10
9
8
7
6
5
4
3
2
1
1 (32 bits)
25 to 18
17
16
15
14
12
L
11
10
9
8
7
6
5
4
3
2
1
Remark
L: Low level
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD70F3107AGJ-UEN-A 制造商:Renesas Electronics 功能描述:V850 50MHz 制造商:Renesas Electronics 功能描述:V850 50MHz Cut Tape
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