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參數(shù)資料
| 型號： | UPD72001GC-A8-3B6 |
| 廠商： | NEC Corp. |
| 英文描述： | MULTI-PROTOCOL SERIAL CONTROLLERS |
| 中文描述： | 多協(xié)議串行控制器 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 206K |
| 代理商： | UPD72001GC-A8-3B6 |
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μ
PD72001-11, 72001-A8
10
(b) Non-vector mode (CR2A: D7 = “0”)
In this mode, the PRI pin controls only the generation of interrupts because the INTAK sequence is not used.
If an interrupt vector output mode other than Type A-3 and Type B-2 is selected, generation of an interrupt
signal is enabled if “L” is input to the PRI pin. The interrupt signal is not generated if “H” is input to PRI.
If an interrupt daisy chain is configured, inputting “L” to this pin indicates that a device having a higher priority
does not acknowledge interrupt processing or does not have an interrupt request, and only the MPSC with
“L” input to its PRI pin can generate an interrupt.
(13)PRO (Priority Output) ... Output
This pin is used when an interrupt daisy chain is configured. This output pin is active-low, and controls generation
of interrupts requests from a device with a lower priority. Usually, this pin is used along with the PRI pin, and
its operation is as follows:
When PRI = “H”, PRO = “H”
When PRI = “L”, PRO goes “H” if there is an interrupt request, and goes “L” if there is no interrupt request.
(14)DRQT
X
A (DMA Request T
X
A) ... Output
This pin outputs a DMA request to a DMA controller. This pin is active-high. It goes “H” if the transmitter of channel
A has entered the T
X
Buffer Empty status. The condition under which this pin goes “H” differs as follows depending
on the setting of the CR1 and D2 bits.
CR1: D2 = “0”: The DRQT
X
A pin goes “H” when the transmitter has entered the T
X
Buffer Empty status after
the first transmit data has been written. It does not go “H” when the transmitter has entered
the T
X
Buffer Empty status after reset.
CR1: D2 = “1”: The DRQT
X
A pin goes “H” when the transmitter has entered the T
X
Buffer Empty status.
This signal is reset when transmit data has been written to channel A.
(15)DRQR
X
A (DMA Request R
X
A) ... Output
This pin outputs a DMA request to a DMA controller. This pin is active-high and goes “H” if the receiver of channel
A has entered the R
X
Character Available status. This signal is reset only when receive data has been read from
channel A.
(16)DTRA/DRQT
X
B (Data Terminal Ready A/DMA Request T
X
B) ... Output
The function of this pin is changed as follows depending on the setting of CR2A: D1 and D0.
(a) When CR2A: D1, D0 = “0, 0” or “0, 1”
This pin functions as the DTRA pin. This pin is a general-purpose output pin and can be used to control a
modem, etc. The operation of the DTRA pin is as follows:
When CR5A: D7 = “0”, DTRA = “H”
When CR5A: D7 = “1”, DTRA = “L”
(b) When CR2A: D1, D0 = “1, 0”
This pin functions as the DRQT
X
B output pin. The function of this pin is the same as the DRQT
X
A pin, except
this pin is used with channel B.
(17)DTRB/DRQR
X
B (Data Terminal Ready B/DMA Request R
X
B) ... Output
The function of this pin changes as follows depending on the setting of CR2A: D1 and D0.
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