參數(shù)資料
型號: UPD72012GB-003
廠商: NEC Corp.
英文描述: HUB CONTROLLER FOR UNIVERSAL SERIAL BUS
中文描述: 集線器控制器通用串行總線
文件頁數(shù): 11/36頁
文件大?。?/td> 414K
代理商: UPD72012GB-003
Data Sheet S13918EJ3V0DS
11
μ
PD72012
1.3 Equivalent Circuits of Pins
Type
Equivalent Circuit
Pins
Function
5 V tolerant
input pin
(Schmitt)
5 V Schmitt on-chip
RST, CS1 to CS5
3.3 V Schmitt input pin with 5 V tolerant.
5 V tolerant
input pin
5 V
CLKSEL, PSSEL,
PVSEL
3.3 V input pin with 5 V tolerant.
5 V tolerant
clock input
pin
5 V
X1, CLK/X2
3.3 V dedicated clock input pin with 5 V
tolerant.
5 V tolerant
3.3 V output
pin
3.3 V, I
OL
=6 mA
OSL
3.3 V output pin with 5 V tolerant.
Pull-up to 5 V line is possible.
Open-drain
output pin
PP1 to PP5
Open-drain structure pin.
USB buffer
IN/OUT(D+)
(D
)
RxDATA
RxSE0
TxDATA
UD0, UD1, D10 to
D50, D11 to D51
USB buffer. The two kinds of receiver are
DATA receiver and SE0 (single end 0) receiver
on the receiving side.
On the sending side, rise and fall times are
managed in the last stage of the buffer in
order to create a difference between low-speed
and full-speed.
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